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low cost, low power cmos general-purpose dual analog front end ad73322l rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures t w o 16-bit a/d c o n v er ters t w o 16-bit d/a c o n v er ters p r ogr a mmable input/output s a mple r a t e s 78 db a d c s n r 78 db d a c s n r 64 khz ma xim u m sample r a te ?90 db crosstalk l o w group dela y (2 5 s t y p p e r ad c channel , 50 s t y p per d a c channel) p r ogr a mmable input/output gain f l e x ible seria l por t allow s up to 4 d u al c o dec s to be c o nnec t ed in c a sc ade , giving 8 i/o channels single -sup ply oper a t ion (2.7 v t o 3.3 v ) 50 mw t y p po w e r c o nsumption a t 3.0 v t e mper a t ure r a nge: ?40 c t o + 105c o n - c h i p re f e re n c e 28-lea d soic, tssop , and 4 4 -l ead l q fp pack ages applic a t io ns g e ner a l - purpose analog i/o speech pr oc ess i ng c o r d less an d p e rsonal c o mmunic a tions te l e p h o n y a c tiv e c o ntro l o f so und and vi br a t io n da ta c o mmuni c a tions w i reless loc a l l oop gener a l description the ad73322 l is a d u al f r o n t-end p r o c es s o r f o r g e n e ral- p u r p ose a p p l ica t i o n s , in c l ud in g s p eec h a n d t e lep h o n y . i t fe a t ur es t w o 16- b i t a/d co n v ersio n cha n nels a nd tw o 16 -b i t d/a con v ersion cha nnels. e a ch cha nnel p r o v i d es 78 db sig n a l - to -n o i s e r a t i o o v er a vo ice-b a nd sig n a l b a ndwi d t h . i t a l s o fe a t ur es a n in p u t-t o -o ut p u t ga in n e tw o r k i n b o t h t h e a n a l og a nd d i g i t a l do m a in s. this is fe a t ur e d o n b o t h c o de cs an d ca n b e u s e d for i m p e da nc e ma tch i ng or s c a l i n g w h e n i n te r f a c i n g to s u bs cr ib er li n e i n t e r f ac e cir c ui ts (s li cs). the ad73322 l is p a r t ic u l a r l y s u i t a b l e f o r a va r i ety o f a p p l i- ca t i o n s i n t h e sp e e c h and te leph on y a r e a , i n cl u d in g l o w b i t ra te , hig h qu a l ity c o m p re ss ion, sp e e ch e n hanc e m e n t, re c o g n i t ion , a nd syn t h e sis. th e lo w g r o u p dela y c h a r ac t e r i s t ic o f th e p a r t mak e s i t s u i t a b l e fo r sin g le o r m u l t ic ha nne l ac ti v e co n t r o l ap p l i c at i o n s . func ti on a l bl ock di a g r a m sdofs adc channel 1 reference dac channel 1 adc channel 2 dac channel 2 sport avdd1 avdd2 dvdd vfbp1 vinp1 vinn1 vfbn1 vfbp2 vinp2 vinn2 vfbn2 voutp2 voutn2 agnd1 agnd2 dgnd sdo mclk reset se sclk sdifs sdi ad73322l 00691-001 voutp1 voutn1 refcap refout fi g u r e 1 . the a/ d an d d / a con v ersio n cha nne ls fe a t ur e p r og ra mma b l e in p u t/o u t p ut ga in s wi t h r a n g es o f 38 db a nd 21 db , r e sp e c t i vely . an o n -chi p r e fer e n c e v o l t a g e al l o ws sin g le -s up pl y o p era t io n. the s a m p l i n g ra t e o f t h e co de cs is p r og ra mma b l e w i t h fo ur s e p a ra t e s e t t in gs o f f e r i n g 64 kh z, 32 kh z, 16 kh z, and 8 kh z s a m p ling ra t e s ( f r o m a mas t er clo c k o f 16.384 mh z). a s e r i al p o r t (s po r t ) al lo ws e a sy in t e r f ac in g o f sin g le o r cas c ade d de v i ce s t o ind u s t r y -s t a nda r d ds p eng i n e s. th e sp or t t r ans f e r r a te i s pro g r a mmabl e to a l l o w i n te r f a c i n g to b o t h f a st and sl o w d s p e n g i ne s . the ad73322 l is a v a i la b l e in 28-lead so i c , 28-lead tsso p , a nd 44-le a d lqf p p a cka g es.
ad73322l* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-211: the alexander current-feedback audio power amplifier ? an-327: dac ics: how many bits is enough? data sheet ? ad73322l: low cost, low power cmos general purpose dual analog front end data sheet reference materials technical articles ? benchmarking integrated audio: why cpu usage alone no longer predicts user experience design resources ? ad73322l material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad73322l engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad73322l rev. a | page 2 of 48 table of contents specifications ..................................................................................... 4 current summary ......................................................................... 6 signal ranges ................................................................................ 7 timing characteristics ................................................................ 7 timing diagrams .......................................................................... 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configurations and function descriptions ......................... 10 ter mi nolo g y .................................................................................... 12 abbreviations .............................................................................. 12 typical performance characteristics and functional block diagram ........................................................................................... 13 functional descriptions ................................................................ 14 encoder channels ...................................................................... 14 programmable gain amplifier ................................................. 14 adc ............................................................................................. 14 analog sigma-delta modulator ............................................... 14 decimation filter ........................................................................ 15 adc coding ............................................................................... 15 decoder channel ........................................................................ 16 dac coding ................................................................................ 16 interpolation filter ..................................................................... 16 analog smoothing filter and pga .......................................... 16 differential output amplifiers ................................................. 16 volt age reference ....................................................................... 16 analog and digital gain taps ................................................... 17 digital gain tap .......................................................................... 18 serial port (sport) ................................................................... 18 sport overview ........................................................................ 18 sport register maps ................................................................ 19 master clock divider ................................................................. 19 serial clock rate divider .......................................................... 19 sample rate divider ................................................................... 19 dac advance register .............................................................. 20 control register a ..................................................................... 21 control register b ...................................................................... 21 control register c ...................................................................... 21 control register d ..................................................................... 22 control register e ...................................................................... 22 control register f ...................................................................... 22 control register g ..................................................................... 23 control register h ..................................................................... 23 operation ......................................................................................... 24 resetting the ad73322l ........................................................... 24 power management ................................................................... 24 operating modes ........................................................................ 24 program (control) mode .......................................................... 24 data mode ................................................................................... 25 mixed program/data mode ...................................................... 25 digital loop-back mode ........................................................... 25 sport loop-back mode .......................................................... 25 analog loop-back mode .......................................................... 26 interfacing ....................................................................................... 27 cascade operation ..................................................................... 27 performance .................................................................................... 29 encoder section .......................................................................... 29 encoder group delay ................................................................ 30 decoder section ......................................................................... 30 on-chip filtering ....................................................................... 31 decoder group delay ................................................................ 31 design considerations ................................................................... 32 analog inputs ............................................................................. 32 interfacing to an electret microphone .................................... 34
ad73322l rev. a | page 3 of 48 analog output .............................................................................34 differential-to-single-ended output .......................................35 digital interfacing .......................................................................35 cascade operation ......................................................................35 grounding and layout ...............................................................36 dsp programming considerations ..............................................37 dsp sport configuration .......................................................37 dsp sport interrupts ...............................................................37 dsp software considerations when interfacing to the ad73322l ....................................................................................37 operating mode ..........................................................................37 mixed-mode operation .............................................................37 interrupts .....................................................................................37 initialization .................................................................................38 running the ad73322l with adcs or dacs in power-down .......................................................................................................38 dac timing control example .....................................................40 configuring an ad73322l to operate in data mode ...............41 configuring an ad73322l to operate in mixed mode ............43 outline dimensions ........................................................................46 ordering guide ...........................................................................47 revision history 12/04rev. 0 to rev. a updated format.................................................................. universal updated outline dimensions........................................................46 changes to ordering guide...........................................................47 4/01revision 0: initial version
ad73322l rev. a | page 4 of 48 specifications avdd = 3 v 10%; dvdd = 3 v 10%; dgnd = agnd = 0 v, f dmclk = 16.384 mhz, f samp = 8 khz; t a = t min to t max , unless otherwise noted. operating temperature range as follows: a grade, t min = ?40c, t max = +85c; y grade, t min = ?40c, t max = +105c. table 1. a and y versions parameter min typ max unit test conditions/comments reference refcap absolute voltage, vrefcap 1.08 1.2 1.32 v refcap tc 50 ppm/c 0.1 f capacitor required from refcap to agnd2 refout typical output impedance 130 ? absolute voltage, v refout 1.08 1.2 1.32 v unloaded minimum load resistance 1 k? maximum load capacitance 100 pf input amplifier offset 1.0 mv maximum output swing 1.578 v max output swing = (1.578/1.2) vrefcap feedback resistance 50 k? f c = 32 khz feedback capacitance 100 pf analog gain tap gain at maximum setting +1 gain at minimum setting ?1 gain resolution 5 bits gain step size = 0.0625 gain accuracy 1.0 % output unloaded settling time 1.0 s tap gain change of ?fs to +fs delay 0.5 s adc specifications dac unloaded maximum input range at vin 1 , 2 1.578 v p-p measured differentially ?2.85 dbm max input = (1.578/1.2) vrefcap nominal reference level at vin 1.0954 v p-p measured differentially (0 dbm0) ?6.02 dbm absolute gain pga = 0 db ?2.0 ?0.7 +0.5 db 1.0 khz, 0 dbm0 gain tracking error 0.1 db 1.0 khz, +3 dbm0 to ?50 dbm0 signal-to-noise and distortion refer to figure 9 pga = 0 db 70 78 db 300 hz to 3400 hz; f samp = 8 khz, puia = 0 79 db 300 hz to 3400 hz; f samp = 8 khz, puia = 1 77.5 db 0 hz to f samp /2; f samp = 8 khz total harmonic distortion pga = 0 db ?86 ?75 db 300 hz to 3400 hz; f samp = 8 khz intermodulation distortion ?61 db pga = 0 db idle channel noise crosstalk ?72 dbm0 pga = 0 db adc-to-dac ?107 db adc input signal level: 1.0 khz, 0 dbm0 dac input at idle adc-to-adc ?92 db adc1 input signal level: 1.0 khz, 0 dbm0 adc2 input at idle; input amplifiers bypassed ?93 db input amplifiers included in input channel dc offset ?20 0 +20 mv pga = 0 db power supply rejection ratio ?65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave
ad73322l rev. a | page 5 of 48 a and y versions parameter min typ max unit test conditions/comments group delay 3 , 4 25 s input resistance at pga 1, 3, 5 20 k? input amplifiers bypassed digital gain tap gain at maximum setting 1 gain at minimum setting ?1 gain resolution 16 bits tested to 5 msb of settings delay 25 s includes dac delay settling time 100 s tap gain change from ?fs to +fs; includes dac settling time dac specifications dac unloaded maximum voltage output swing 1 single-ended 1.578 v p-p pga = 6 db ?2.85 dbm max output = (1.578/1.2) vrefcap differential 3.156 v p-p pga = 6 db 3.17 dbm max output = 2 (1.578/1.2) vrefcap nominal voltage output swing (0 dbm0) single-ended 1.0954 v p-p pga = 6 db ?6.02 dbm differential 2.1909 v p-p pga = 6 db 0 dbm output bias voltage 1.2 v refout unloaded absolute gain ?1.75 ?0.6 +0.75 db 1.0 khz, 0 dbm0; unloaded gain tracking error 0.1 db 1.0 khz, +3 dbm0 to ?50 dbm0 signal-to-noise and distortion at 0 dbm0 refer to figure 10 pga = 0 db 72 78.5 db 300 hz to 3400 hz; f samp = 8 khz total harmonic distortion at 0 dbm0 pga = 0 db ?89 ?75 db 300 hz to 3400 hz; f samp = 8 khz intermodulation distortion ?77 db pga = 0 db idle channel noise crosstalk ?81 dbm0 pga = 0 db dac-to-adc ?73 db adc input signal level: agnd; dac output signal level: 1.0 khz, 0 dbm0 input amplifiers bypassed ?74 db input amplifiers included in input channel dac-to-dac ?102 db dac1 output signal level: agnd; dac2 output signal level: 1.0 khz, 0 dbm0 power supply rejection ?65 db input signal level at avdd and dvdd pins: 1.0 khz, 100 mv p-p sine wave group delay 3, 4 25 s interpolator bypassed 50 s output dc offset 1, 6 ?50 +5 +60 mv minimum load resistance, r l 1, 7 single-ended 3 150 ? differential 150 ? maximum load capacitance, c l 1, 7 single-ended 500 pf differential 100 pf frequency response (adc and dac) 8 typical output frequency (normalized to fs) 0 0 db 0.03125 ?0.1 db
ad73322l rev. a | page 6 of 48 a and y versions parameter min typ max unit test conditions/comments 0.0625 ?0.25 db 0.125 ?0.6 db 0.1875 ?1.4 db 0.25 ?2.8 db 0.3125 ? 4.5 db 0.375 ?7.0 db 0.4375 ?9.5 db > 0.5 ad73322l rev. a | page 7 of 48 signal ranges table 3. mnemoic description range vrefcap 1.2 v 10% vrefout 1.2 v 10% adc maximum input range at v in 1.578 v p-p nominal reference level 1.0954 v p-p dac maximum voltage output swing single-ended 1.578 v p-p differential 3.156 v p-p nominal voltage output swing single-ended 1.0954 v p-p differential 2.1909 v p-p output bias voltage vrefout timing characteristics avdd = 3 v 10%; dvdd = 3 v 10%; agnd = dgnd = 0 v; t a = t mln to t max , unless otherwise noted. table 4. parameter limit at t a = ? 40c to +105c unit description clock signals see figure 2 t 1 61 ns min mclk period t 2 24.4 ns min mclk width high t 3 24.4 ns min mclk width low serial port see figure 4 and figure 5 t 4 t 1 ns min sclk period t 5 0.4 t 1 ns min sclk width high t 6 0.4 t 1 ns min sclk width low t 7 20 ns min sdi/sdifs setup before sclk low t 8 0 ns min sdi/sdifs hold after sclk low t 9 10 ns max sdofs delay from sclk high t 10 10 ns min sdofs hold after sclk high t 11 10 ns min sdo hold after sclk high t 12 10 ns max sdo delay from sclk high t 13 30 ns max sclk delay from mclk
ad73322l r e v. a | pa ge 8 o f 4 8 timing dia g r a ms 00691-002 t 1 t 2 t 3 fi g u r e 2 . m c l k t i m i n g 00691-003 100 ai ol 100 ai oh 2.1v to output pin c l 15pf f i g u re 3. l o ad ci r c uit f o r tim i ng spec i f ic at ions * sclk is individually programmable in frequency (mclk/4 shown here). mclk sclk* 00691-004 t 1 t 2 t 3 t 13 t 5 t 6 t 4 fi g u r e 4 . s c l k t i m i n g se (i) sclk (o) sdifs (i) sdi (i) sdofs (o) sdo (o) three- state three- state three- state d15 d2 d1 d0 d14 d15 d0 d1 d14 d15 d15 00691-005 t 7 t 9 t 8 t 10 t 12 t 11 t 7 t 8 f i gure 5. s e ri al p o r t (spor t )
ad73322l r e v. a | pa ge 9 o f 4 8 absolute maximum ra tings t a = 2 5 c u n l e s s ot he r w i s e not e d. table 5. p a r a me t e r s r a t i n g s a v dd , dvd d to gnd ?0.3 v to +4.6 v a g nd t o dg nd ?0.3 v t o +0.3 v digital i/o v o lta g e to dgnd ?0.3 v to ( d vdd + 0.3 v ) analog i/o v o lta g e to a g nd ?0.3 v to ( a vdd + 0.3 v ) o p era t ing t e mp er a tur e r a nge i n dustr i al ( a v e r s ion) ?40c to +85c ex tended ( y v e rsion) ?40c to +105c stor age t e mpera tur e r a nge ?65c to +150c m a ximum junc tion t e mpera tur e 150c soic, ja ther m a l i m pedanc e 71.4c/w l e ad t e mper a tur e , s o lder ing v a por p h ase (60 sec) 215c i n fr ar ed (15 sec) 220c l q fp , ja ther m a l i m pedanc e 53.2c/w l e ad t e mper a tur e , s o lder ing v a por p h ase (60 sec) 215c i n fr ar ed (15 sec) 220c tssop , ja thermal i m pedanc e 97.9c/w l e ad t e mper a tur e , s o lder ing v a por p h ase (60 sec) 215c i n fr ar ed (15 sec) 220c s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xim u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h os e list e d i n t h e op era t io nal s e c t ion s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr os ta tic char g e s as high as 4000 v r e adily ac cumula te on the uman body and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr odu c t f e a tur es pr o p r i etar y esd pr otec tio n cir c u i tr y , per m anen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g es . ther ef o r e , p r ope r esd pr ecaution s ar e r e c o mmended to a v oid per f or m a nc e degrada t ion or l o ss of func tiona l it y .
ad73322l rev. a | page 10 of 48 pin conf igura t ions and f u ncti on descriptions 00691-006 vfbn2 28 vinn2 27 vfbp2 26 vinp2 25 voutn1 24 voutp1 23 voutn2 22 voutp2 21 avdd1 20 agnd1 19 se 18 sdi 17 sdifs 16 sdofs 15 vinp1 1 vfbp1 2 vinn1 3 vfbn1 4 refout 5 refcap 6 avdd2 7 agnd2 8 dgnd 9 dvdd 10 reset 11 sclk 12 mclk 13 sdo 14 ad73322l top view (not to scale) f i g u re 6. 28-l e ad w i de body 00691-007 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ad73322l top view vfbp1 vinn1 vfbn1 avdd2 refcap refout vinp1 vinn2 vfbp2 vinp2 voutn2 voutp1 voutn1 agnd2 dgnd dvdd sdo sclk reset voutp2 avdd1 agnd1 sdofs mclk sdifs sdi se vfbn2 f i g u re 7. 28-l e ad t h in s h ri nk 00691-008 44 nc 43 v f bn1 42 v i nn1 41 vfb p 1 40 vin p 1 39 nc 38 vfb n 2 37 v i nn2 36 vfb p 2 35 vin p 2 34 nc 32 voutn1 31 voutp1 30 nc 27 nc 28 voutp2 29 voutn2 33 nc 26 avdd1 25 avdd1 24 agnd1 23 agnd1 2 refcap 3 avdd2 4 avdd2 7 agnd2 6 agnd2 5 agnd2 1 refout 8 agnd2 9 dgnd 10 dgnd 11 dvdd nc = no connect 12 nc 13 r eset 14 sc lk 15 mclk 16 sd o 17 nc 18 sd ofs 19 sd ifs 20 sd i 21 se 22 nc pin 1 ad73322l top view (not to scale) f i g u re 8. 44-l e ad p l as t i c t h in q u ad f l a t pack ta ble 6. pi n f u nct i on d e s c ri pt i o ns mnemonic f u nc t i o n vinp1 analog i n put t o the in v e r t ing input amplifier on channel 1 s po s i tiv e input. vfbp1 f eedback c o nnec tion fr om the output of the in v e r t ing amplifier on channe l 1 s positi v e input. w h en the input amplifier s ar e b y pass ed , this p i n all o w s d i rec t ac c e s s to the po sitiv e in put of channe l 1 s sigm a - d e lta mod u la tor . vinn1 analog i n put t o the in v e r t ing input amplifier on channel 1 s neg a tiv e in put. vfbn1 f eedback c o nnec tion fr om the output of th e in v e r t ing amplifier on chann e l 1 s n e ga tiv e in put. w h en the input amplifiers ar e b y pass ed , this p i n all o w s d i rec t ac c e s s to the ne ga tiv e in put of channe l 1 s sigma - d e lta mod u la tor . refout buff er ed r e f e r e nc e o utput, which has a n o mina l v a lue of 1.2 v . refc ap a b y pass capacit o r t o a g nd2 of 0.1 f is r e quir ed f o r the on- c hip r e f e renc e . the capacitor shoul d be fix e d to this pin. a v dd2 analog p o w e r s u p p ly c o nne c t ion. a g nd2 analog ground/substra te c o nn ec tion2. dgnd dig i tal gr ound/substr a te c o nnec tion. dvdd dig i tal p o w e r supply c o nnec tion. rese t a c tiv e l o w r e set sig n al . t h is input r e sets the en tir e chip , r e setting the c o n t r o l r e g i st ers and clearing the dig i tal cir c uitr y .
ad73322l rev. a | page 11 of 48 mnemonic function sclk serial clock output. this rate determines the serial transfer rate to/from the codec. it is used to clock data or control information to and from the serial port (s port). the frequency of sclk is equal to the frequency of the master clock (mclk) divided by an integer numberthis integer number being the product of the external master clock rate divider and the serial clock rate divider. mclk master clock input. mclk is dr iven from an external clock signal. sdo serial data output. both data and control information may be output on th is pin and are clocked on the positive edge of sclk. sdo is in three-state when no information is being transmitted and when se is low. sdofs framing signal output for sdo serial transfers. the frame sync is one bit wide and is active one sclk period before the first bit (msb) of each output word. sdofs is referenced to the posit ive edge of sclk. sdofs is in three-state when se is low. sdifs framing signal input for sdi serial transfers. the frame sync is one bit wide and is valid one sclk period before the first bit (msb) of each input word. sdifs is sampled on the nega tive edge of sclk and is ignored when se is low. sdi serial data input. bo th data and control information may be input on this pin and are clocked on the negative edge of sclk. sdi is ignored when se is low. se sport enable. asynchronous input enable pin for the sport. when se is set low by the dsp, the output pins of the sport are three-stated and the input pins are ignored. sclk is also disabled internally in order to decrease power dissipation. when se i s brought high, the control and data registers of the sport are at their original values (before se was brought low); however, the timing counters and other internal registers are at their reset values. agnd1 analog ground/substrate connection. avdd1 analog power supply connection. voutp2 analog output from the positi ve terminal of output channel 2. voutn2 analog output from the negati ve terminal of output channel 2. voutp1 analog output from the positi ve terminal of output channel 1. voutn1 analog output from the negati ve terminal of output channel 1. vinp2 analog input to the inverting input amplifier on channel 2s positive input. vfbp2 feedback connection from the output of th e inverting amplifier on channel 2s positive input. when the input amplifiers are bypassed, this pin allows direct access to the positive input of channel 2s sigma-delta modulator. vinn2 analog input to the inverting input am plifier on channel 2s negative input. vfbn2 feedback connection from the output of th e inverting amplifier on channel 2s negative input. when the input amplifiers are bypassed, this pin allows direct access to the negative input of channel 2s sigma-delta modulator.
ad73322l rev. a | page 12 of 48 terminology absolute gain a measure of converter gain for a known signal. absolute gain is measured (differentially) with a 1 khz sine wave at 0 dbm0 for the dac and with a 1 khz sine wave at 0 dbm0 for the adc. the absolute gain specification is used for gain tracking error specification. crosstalk crosstalk is due to coupling of signals from a given channel to an adjacent channel. it is defined as the ratio of the amplitude of the coupled signal to the amplitude of the input signal. crosstalk is expressed in db. gain tracking error measures changes in converter output for different signal levels relative to an absolute signal level. the absolute signal level is 0 dbm0 (equal to absolute gain) at 1 khz for the dac and 0 dbm0 (equal to absolute gain) at 1 khz for the adc. gain tracking error at 0 dbm0 (adc) and 0 dbm0 (dac) is 0 db by definition. group delay the derivative of radian phase with respect to radian frequency, d?(f)/df. group delay is a measure of the average delay of a system as a function of frequency. a linear system with a constant group delay has a linear phase response. the deviation of group delay from a constant indicates the degree of nonlinear phase response of the system. idle channel noise the total signal energy measured at the output of the device when the input is grounded (measured in the frequency range 300 hz to 3400 hz). intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. intermodulation terms are those for which neither m nor n is equal to zero. for final testing, the second- order terms include (fa + fb) and (fa ? fb), while the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb) and (fa ? 2fb). power supply rejection measures the susceptibility of a device to noise on the power supply. power supply rejection is measured by modulating the power supply with a sine wave and measuring the noise at the output (relative to 0 db). sample rate the rate at which the adc updates its output register and the dac updates its output from its input register. the sample rate can be chosen from a list of four that are fixed relative to the dmclk. sample rate is set by programming bits dir0-1 in control register b of each channel. snr + thd signal-to-noise ratio plus harmonic distortion is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components in the frequency range 300 hz to 3400 hz, including harmonics but excluding dc. abbreviations table 7. abbreviation definition adc analog-to-digital converter. afe analog front end. agt analog gain tap. alb analog loop-back. bw bandwidth. crx a control register where x is a placeholder for an alphabetic character (a to h). there are eight read/write control registers on the ad73322l cra through crh. crx:n a bit position, where n is a placeholder for a numeric character (0 to 7), within a control register, where x is a placeholder for an alphabetic character (a to e). position 7 represents the msb and position 0 represents the lsb. dac digital-to-analog converter. dgt digital gain tap. dlb digital loop-back. dmclk device (internal) master clock. this is the internal master clock resulting from the external master clock (mclk) being divided by the on-chip master clock divider. fs full scale. fslb frame sync loop-backwhere the sdofs of the final device in a cascade is connected to the rfs and tfs of the dsp and the sdifs of first device in the cascade. data input and output occur simultaneously. in the case of nonfslb, sdofs and sdo are connected to the rx port of the dsp while sdifs and sdi are connected to the tx port. pga programmable gain amplifier. sc switched capacitor. slb sport loop-back. snr signal-to-noise ratio. sport serial port. thd total harmonic distortion. vbw voice bandwidth.
ad73322l rev. a | page 13 of 48 typical perf orm ance cha r acte rist ics and functional block diagram 00691-009 v in (dbm0) 5 3.17 ?85 ? 75 ? 6 5 ? 55 ?45 ? 35 ? 2 5 ? 15 ?5 s / (n + d) (db) 80 60 70 50 30 40 10 20 0 ?10 f i gure 9. s / n(n = d ) vs. v in ( a dc @ 3 v ) o v er v o ic e band width (3 00 h z to 3 . 4 khz ) 00691-010 v in (dbm0) 5 3.17 ?85 ? 75 ? 6 5 ? 55 ?45 ? 35 ? 2 5 ? 15 ?5 s / (n + d) (db) 80 60 70 50 30 40 10 20 0 ?10 f i gure 10. s/n( n = d) vs. v in (d a c @ 3 v ) o v er v o ice b a nd width (3 00 h z to 3 . 4 khz ) invert single-ended enable decimator serial i/o port continuous time low-pass filter 1-bit dac switched capacitor low-pass filter digital - ? modulator digital - ? modulator inter- polator v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l agnd1 agnd2 dgnd sdofs sdo mclk se reset sclk sdifs sdi dvdd avdd2 avdd1 analog loop- back +6/15db pga 0/38db pga gain 1 gain 1 invert single-ended enable decimator continuous time low-pass filter 1-bit dac switched capacitor low-pass filter digital - ? modulator digital - ? modulator inter- polator v ref refcap refout reference vfbn2 vinn2 vinp2 vfbp2 voutp2 voutn2 analog loop- back +6/? 15db pga 0/38db pga gain 1 gain 1 00691-011 f i g u re 11. f u nc t i o n al bl ock d i ag r a m
ad73322l rev. a | page 14 of 48 functional descriptions enc o der channels b o t h e n co der cha nne ls co n s ist o f a p a ir o f in v e r t in g o p a m ps w i th f e e d ba ck co n n ect i o n s tha t ca n be b y pa s s e d i f r e q u i r ed , a swi t ch e d ca p a c i t o r pga an d a sig m a- del t a ana l og-t o-d i g i t a l co n v er t e r (ad c ). an o n -bo a r d digi t a l f i l t er , which f o r m s p a r t o f t h e sig m a- de l t a ad c, als o p e r f o r m s cr i t ical sys t em-l e v el f i l t er in g. d u e t o t h e hig h le ve l of o v ers a m p ling, t h e in p u t a n t i al ias r e q u ir em e n ts a r e r e d u c e d s u c h tha t a sim p le sin g l e - p o le r c s t a g e is s u f f i cien t t o g i ve adeq ua t e a t ten u a t ion in t h e b a nd o f in ter e st. progr a mm able gain amplifier e a c h en c o d e r se cti o n s a n al og f r o n t en d c o m p rise s a sw i t c h ed c a pa c i t o r p g a , wh i c h al so f o rm s pa r t o f th e s i g m a - de l t a mo d u l a tor . t h e s c s a m p l i ng f r e q u e nc y i s dmc l k / 8 . t h e pga, w h os e p r og ra mma b l e ga i n s e t t i n gs a r e sho w n i n t a b l e 8, ma y b e us ed t o in cr eas e t h e sig n al leve l a p p l ied t o th e ad c f r om l o w output s o u r c e s su ch a s m i c r opho ne s , an d c a n b e us e d t o a v o i d pl acin g ext e r n a l am plif iers i n t h e cir c ui t. t h e i n p u t s i gn al lev e l t o th e s i gma - d e l t a m o d u la t o r s h o u ld n o t exce e d t h e maxi m u m in p u t v o l t a g e p e r m i t t e d . t h e p g a g a i n i s s e t b y bit s ig s 0 , ig s 1 , an d ig s 2 ( c r d : 0 C 2 ) i n c o n t ro l re g i ste r d . ta ble 8. pga s e t t i ngs for t h e encoder cha n nel i g s 2 i g s 1 i g s 0 g a i n ( d b ) 0 0 0 0 0 0 1 6 0 1 0 1 2 0 1 1 1 8 1 0 0 2 0 1 0 1 2 6 1 1 0 3 2 1 1 1 3 8 adc b o t h a d cs co nsist o f a n a n a l o g sig m a- delt a m o d u l a to r a nd a dig i t a l an t i a l iasi n g de cim a t i on f i l t er . t h e s i g m a - del t a m o d u la tor n o is e - s h a p es t h e sig n al an d p r o d uces 1- b i t s a m p les a t a d m clk/8 ra t e . this b i t s t r e am, r e p r es en t i n g t h e a n alog in pu t sig n al , is i n p u t to t h e an t i al iasi ng de cima t i o n f i l t er . th e de cim a t i o n f i lte r r e d u ces t h e s a m p le r a te a nd i n cr e a s e s t h e re s o lut i on . anal og sig m a - del t a modul a t o r the ad73322l s in p u t c h a n ne ls em p l o y a sig m a-del t a co n v ersio n t e c h niq u e , which p r o v ides a hig h r e s o l u tio n 16-b i t o u t p u t wi t h sys t em f i l t er ing bein g im p l em en te d o n -chi p . sig m a- d e l t a co n v er t e rs em plo y a t e chn i q u e k n o w n as o v ers a m p li n g , w h er e t h e s a m p lin g ra te is man y t i m e s t h e hig h es t f r eq uenc y o f in t e r e s t . i n th e cas e o f t h e ad73322l, t h e ini t i a l s a m p l i n g ra t e o f t h e sig m a-d e l t a m o d u l a to r is d m clk/8 . the ma i n ef fe c t o f o v ers a m p ling is t h a t t h e q u an t i za t i on n o is e i s s p r e ad o v er a v e r y wide band wid t h, u p t o f s /2 = d m clk/16 (f igur e 13). thi s m e an s t h a t t h e n o is e in t h e b a nd o f in t e r e st is m u c h r e d u ced . an o t h e r co m p l e m e n t a r y f e a t ure o f sig m a-de l t a co n v er t e rs is t h e us e o f a t e chni q u e cal l e d n o is e - s h a p ing. this t e chni q u e has t h e ef fe c t o f p u s h in g t h e n o is e f r o m t h e b a n d o f in t e r e st t o a n out-o f -b and p o si t i o n (f igur e 14). the com b in - a t io n o f t h es e t e chniq u es, fol l o w e d b y t h e a p pl ica t io n o f a dig i t a l f i l t er , s u f f icien t l y r e d u ce s t h e n o i s e i n b a nd t o en s u r e g o o d d y na mic p e r f o r ma n c e f r o m t h e p a r t (f i g ur e 15). f s /2 dmclk/16 digital filter noise shaping a. 00691-012 band of interest f s /2 dmclk/16 b. band of interest f s /2 dmclk/16 c. band of interest f i gur e 1 2 . si g m a-d e l t a noi s e re duction f i g u re 1 3 t h rou g h f i g u re 1 6 s h o w t h e v a r i ou s s t age s of f i lte r i n g tha t a r e em p l o y ed in a typ i c a l ad73322l a p p l ica t io n. f i gur e 1 3 s h o w s t h e t r an sfer f u n c t i on o f t h e ext e r n al a n al og a n t i al ias f i l t er . e v en t h o u g h i t is a sing le r c p o le , i t s c u to f f f r eq uen c y i s s u ffi c i e n t l y f a r a w a y fr o m th e i n i t i a l s a m p l i n g fr e q u e n c y (d mclk/8) tha t i t tak e s ca r e o f a n y sig n als tha t co u l d be al i a sed b y t h e sa m p l i n g f r eq u e n c y . t h i s al so s h o w s t h e ma jo r dif f er en ce b e twe e n t h e ini t i a l o v ers a m p ling r a te a nd t h e b a nd- w i d t h of i n te re s t . in f i g u re 1 4 , t h e s i g n a l a n d n o i s e - sh a p i n g r e s p o n s e s o f t h e sig m a-de l t a m o d u l a t o r a r e sh o w n. th e s i g n a l re sp ons e pro v i d e s f u r t he r re j e c t i o n of a n y h i g h f r e q uen c y sig n als, while t h e n o is e-sha p in g p u shes th e in h e r e n t q u a n tiz a ti o n n o i s e t o a n o u t - o f -ba n d posi ti o n . t h e d e ta il o f
ad73322l rev. a | page 15 of 48 f i gur e 15 sh o w s th e r e spo n se o f th e d i g i tal d e cim a ti o n f i l t e r (sin c-c u bed r e sp o n se) wi th n u lls ev er y m u l t i p le o f d m clk/25 6 co r r es p o n d in g to t h e de cima t i on f i l t er u p da t e r a t e fo r a 64 kh z s a m p ling. th e n u l l s o f t h e si n c 3 r e s p o n s e co r r esp o nd wi t h m u l t i p les o f t h e ch o s e n s a m p l i ng f r e q uen c y . t h e f i na l det a i l i n f i gur e 16 sh o w s t h e a p pli c a t io n o f a f i nal a n t i al i a s f i l t er in t h e ds p en g i ne . this has t h e ad v a n t a g e o f b e in g i m plem e n t e d acco r d in g t o t h e us er s r e q u ir e m e n ts and a v a i l a b l e mips. the f i l t er in g in f i gu r e 13 thr o ug h f i gur e 16 is im p l em en t e d in t h e ad73322l. f i gur e 13 t o f i g u r e 16 s h o w ad c f r eq uen c y r e s p o n s e s. f b = 4khz f sinit = dmclk/8 00691-013 f i g u re 13. a n a l og a n t i al ias f i lte r t r an s f er f u nc t i on noise transfer function signal transfer function 00691-014 f b = 4khz f sinit = dmclk/8 f i gur e 1 4 . a n al o g si gma-del t a m o dula t o r t r ansfe r f u nct i o n 00691-015 f b = 4khz f sinter = dmclk/256 f i gure 15. d i g i tal d eci m a to r t r a n sfer f u nc tio n 00691-016 f b = 4khz f srnal = 8khz f sinter = dmclk/256 f i g u re 16. f i n a l f ilt er ( h pf) t r ans f er f u nc t i on decima t i o n fil t er the dig i t a l f i l t er us ed in t h e ad73322l ca r r i es o u t tw o im p o r t an t f u n c t i o n s. f i rst, i t r e m o v e s t h e o u t-of-b a nd q u an t i za t i on n o is e , w h ich is sha p e d b y t h e a n a l og m o d u la t o r a nd s e cond , i t d e cima tes t h e h i g h f r e q uen c y b i t st r e a m to a lo w e r ra t e , 16-b i t w o r d . the a n t i al iasin g de cima t i o n f i l t er is a sin c -c ub e d dig i t a l f i l t er tha t r e d u ces t h e s a m p lin g r a t e f r o m d m clk/8 t o d m clk/256 , an d i n c r e a s e s t h e re s o lut i on f r om a s i ng l e bit to 1 5 bit s or gr ea t e r (d e p en di n g o n ch osen s a m p l i n g ra t e ). i t s z tra n s f o r m i s gi v e n a s [(1 ? z ? n )/(1 ? z ?1 )] 3 w h er e n is s e t b y th e s a m p ling ra t e ( n = 32 @ 64 kh z s a m p lin g n = 256 @ 8 kh z s a m p ling) th us, w h e n t h e s a m p ling ra t e is 64 khz, a m i n i ma l g r o u p dela y o f 25 s ca n be ac hiev e d . w o r d gr o w th i n th e d e ci ma t o r is d e t e rmin ed b y th e sa m p lin g ra t e . a t 64 kh z s a m p ling, w h er e t h e o v ers a m p lin g ra t i o (osr) b e tw e e n sig m a- del t a m o d u l a to r a nd de ci ma to r o u t p ut e q u a ls 32, t h er e a r e f i ve b i ts p e r s t a g e o f t h e t h r e e-s t ag e sin c3 f i l t er . d u e t o symm et r y wi t h i n t h e si g m a-de l t a m o d u la t o r , t h e l s b is al wa ys a zer o ; t h er efo r e , t h e 1 6 -b i t ad c o u t p u t w o r d has 2 ls bs e q u a l t o zer o , on e d u e t o t h e s i g m a- de l t a symmet r y a n d t h e ot h e r b e in g a p a dd in g zer o to ma k e u p t h e 1 6 -b i t w o r d . a t lo w e r sa m p lin g ra t e s, d e cima t o r w o r d gr o w th i s gr ea t e r th a n th e 16- b i t sa m p le w o r d , th e r e f o r e tr un ca ti o n occur s i n tra n sf e r ri n g t h e de cima t o r ou t p ut as t h e a d c w o r d . f o r exa m ple , a t 8 kh z s a m p ling, w o r d g r o w th r e ach e s 24 b i ts d u e t o t h e os r o f 256 b e tw e e n t h e sig m a-d e lt a m o d u l a to r a nd de c i m a to r o u t p ut. this yie l ds 8 b i t s p e r s t a g e o f t h e t h r e e-s t a g e si n c 3 f i l t er . adc c o ding the ad c co ding s c h e me is in tw os co m p lem e n t f o r m a t , as s h o w n i n f i gur e 17). th e ou t p u t w o r d s a r e fo r m e d b y t h e d e ci ma ti o n f i l t er , wh i c h gr o w s t h e w o r d len g th f r o m th e sin g le b i t o u t p u t o f t h e sig m a- delt a m o d u l a t o r t o a w o rd len g t h o f u p to 24 b i ts ( d ep e ndin g on de c i m a t i o n r a te ch o s e n ), w h ich is t h e f i n a l output of t h e a d c bl o c k . i n d a t a mo d e t h i s v a lu e i s t r u n - c a te d to 1 6 bit s f o r output on t h e s e r i a l d a t a output ( s d o ) pi n . v ref + (v ref 0.32875) v ref v ref ? (v ref 0.32875) 10...00 00...00 01...11 adc code differential analog input analog input v inn v inp v ref + (v ref 0.6575) v ref ? ( v ref 0.6575) 10...00 00...00 01...11 adc code single-ended v inp v inn 00691-017 f i gur e 1 7 . adc t r ansfe r f u ncti on
ad73322l rev. a | page 16 of 48 i n m i xe d co n t r o l/ da t a m o d e , t h e r e s o l u t i o n is f i xe d a t 15 b i ts, w i th t h e ms b o f th e 16- b i t tra n sf e r be i n g used a s a f l a g b i t t o i n d i c a t e e i th e r co n t r o l o r d a ta i n th e fr a m e . dec o der c h an nel the de co der ch a nnels co n s ist of dig i t a l i n ter p o l a t o r s, dig i t a l s i gm a - d e l t a m o d u la t o r s , s i n g le b i t d i g i tal- t o - a nal o g c o n v e r t e r s (d a c ), a n alog sm o o t h ing f i l t er s a nd p r ogra mma b l e ga in a m plif iers wi t h dif f er en t i a l o u t p u t s. da c c o d i n g the d a c co ding s c h e me is in tw os co m p lem e n t f o r m a t wi th 0x7fff bein g f u ll-scale p o si ti ve a nd 0x8000 bein g f u ll-s cale ne g a t i ve . interpol a t io n fil t er the a n t i - i m a g i n g in t e r p ola t io n f i l t er is a si n c - c ub e d dig i t a l f i l t er t h a t u p - s am ples t h e 16- b i t in p u t w o r d s f r o m t h e i n p u t s a m p l e r a t e to a r a te of d m c l k / 8 , w h i l e f i lte r i n g to a t t e n u a t e ima g es p r o d uce d b y t h e in t e r p ola t ion p r o c ess. i t s z t r a n sfo r m is gi v e n a s [(1 ? z ? n )/(1 ? z ?1 )] 3 w h er e n is det e r m ined b y t h e s a m p ling ra t e ( n = 32 @ 64 kh z . . . n = 256 @ 8 kh z) the d a c r e cei ves 16-b i t s a m p le s f r o m t h e h o s t ds p p r o c es s o r a t t h e p r og ra mm e d s a m p le r a te o f d m clk/n. i f the h o st p r o c es s o r fa i l s to wr i t e a n e w v a l u e t o t h e s e r i a l p o r t , t h e exis tin g (p r e vious) da t a is r e ad a g a i n. th e da t a s t r e a m is f i l t er e d b y t h e an t i - i mag i n g i n t e r p ol a t i o n f i l t er , b u t t h e r e is a n o p t i on to b y p a s s t h e in ter p ola t o r fo r t h e mini m u m g r o u p dela y co nf igura t io n b y s e t t in g t h e ib yp b i t (cre:5) o f c o n t r o l reg i st er e. th e in t e r p ol a t ion f i l t er has t h e s a m e cha r ac t e r i s t ics a s th e a d c s a n ti ali a sin g d e ci ma ti o n f i l t e r . the o u t p u t o f t h e in t e r p ola t ion f i l t er is fe d t o t h e d a c s dig i t a l sig m a- de lt a m o d u l a t o r , w h ich c o n v er ts t h e 16- b i t da t a t o 1-b i t s a m p les a t a ra te o f d m clk/8. the m o d u la t o r n o is e - s h a p es t h e sig n al s o tha t er r o rs inh e r e n t t o th e p r o c es s a r e minimize d in t h e p a ss b a n d o f t h e con v er t e r . the b i t- s t r e a m o u t p ut o f t h e sig m a- de l t a m o d u l a t o r is fe d t o t h e s i n g le b i t d a c w h er e i t is c o n v e r te d to an an a l o g volt age. anal og sm oo thing fil t er and pga t h e output of t h e s i ng l e bit d a c i s s a m p l e d a t dm c l k / 8 , t h er efo r e i t is n e ces s a r y t o f i l t er t h e ou t p u t t o r e co n s t r uc t t h e lo w f r e q uen c y sig n a l . t h e de co der s a n a l o g s m o o t h ing f i l t er co n s is ts o f a con t in uo us-time f i l t er p r ecede d b y a thir d-o r der swi t ch e d -c a p aci t o r f i l t er . the con t i n uo us-t i m e f i l t er fo r m s p a r t o f t h e o u t p u t p r og ra mma ble ga in am plif ie r (pga). the pga ca n b e us ed t o ad j u s t th e ou t p u t sig n a l lev e l f r o m ?15 db t o +6 db in 3 db s t eps, as s h o w n in t a ble 9. th e pg a g a i n i s s e t b y b i t s og s 0 , og s 1 , a n d og s 2 ( c r d : 4 - 6 ) i n co n t r o l r e g i s t e r d . ta ble 9. pga s e t t i ngs for t h e decoder cha n nel o g s 2 o g s 1 o g s 0 g a i n ( d b ) 0 0 0 + 6 0 0 1 + 3 0 1 0 0 0 1 1 ? 3 1 0 0 ? 6 1 0 1 ? 9 1 1 0 ? 12 1 1 1 ? 15 differential output amplifiers the de co der has a dif f er en t i al analog o u t p u t p a ir (v o u tp an d v o u t n). t h e o u t p ut cha n nel ca n b e m u te d b y s e t t i n g t h e mute b i t (crd:7) in c o n t r o l reg i st er d . th e o u t p u t sig n al is dc-b ia s e d to t h e co de c s on-ch i p vol t a g e r e fer e nce. v o l t a g e reference the ad73322 l r e f e r e n c e , ref c ap , is a ban d ga p r e f e r e n c e tha t p r o v ide s a lo w n o is e, t e m p era t ur e-co m p en s a t e d r e fer e n c e t o t h e d a c and ad c. a b u f f er e d v e rsio n o f t h e r e fer e n c e is als o made a v a i la b l e o n t h e ref o ut pin, and can b e us e d to b i a s o t h e r e x te r n a l an a l o g c i rc u i t r y . t h e re f e re nc e h a s a d e f a u l t nom i n a l val u e o f 1.2 v . the r e fer e n c e ou t p ut (refo u t) can b e ena b l e d fo r b i asi n g e x te r n a l c i rc u i t r y b y s e tt i n g t h e r u bi t ( c r c : 6 ) of c r c . inverting op amps analog gain tap analog loop-back select invert single- ended enable 00691-018 continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/? 15db pga 0/38db pga gain 1 refcap refout reference v ref f i gure 1 8 . a n al o g input/ o u tput sect io n
ad73322l rev. a | page 17 of 48 mclk divider mclk external se reset sdifs sdi serial port 1 (sport 1) serial register 1 sclk divider sclk control register 1a control register 1b control register 1g control register 1h control register 1f control register 1c control register 1d dmclk internal sdofs1 sdo1 00691-019 8 3 3 16 8 2 8 8 8 8 control register 1e mclk divider mclk external se reset sdifs2 sdi2 serial port 2 (sport 1) serial register 2 sclk divider sclk control register 2a control register 2b control register 2g control register 2h control register 2f control register 2c control register 2d dmclk internal sdofs sdo 8 16 8 2 8 8 8 8 control register 2e f i g u re 19. sport bl ock d i ag r a m anal og a n d dig i t a l g a in t a ps the ad73322 l f e a t ur es a n alog a nd dig i t a l f eedbac k p a t h s b e t w e e n i n put a n d output . t h e amou n t of f e e d b a ck i s d e te r - mi n e d b y t h e gain s e t t in g w h ich is p r og ra mm e d in t h e con t r o l r e g i s t ers. this fe a t ur e can typ i c a l l y b e us e d fo r b a lan c i n g t h e ef fe c t i v e im p e da n c e b e twe e n in p u t an d o u t p ut w h en us e d i n s u bs cr ib er li n e i n t e r f ac e cir c ui t (s li c) in t e r f aci n g. analog gain tap the a n alog ga in ta p is co nf igur ed as a p r og ra mma b l e dif f er en t i a l a m plif ier w h os e i n pu t is t a k e n f r o m t h e ad c s in p u t sig n a l p a t h . t h e o u t p u t o f t h e ana l og ga in t a p is sum m e d wi t h t h e o u t p u t o f t h e d a c. the ga in is p r og ra mma b l e usin g c o n t r o l reg i s t er f (crf:0-4) t o ac hieve a ga in o f ?1 t o +1 in 32 s t eps wi t h m u tin g bein g ac hiev ed t h r o ug h a s e p a ra t e con t r o l s e t t in g ( c o n t r ol reg i st er f bi t 7 ) . the ga in i n cr em e n t p e r s t ep is 0.0625. th e a g t is enab led b y p o w e r i n g -u p t h e a g t con t r o l b i t in t h e p o wer co n t r o l r e g i st er (crc:1). w h e n t h is b i t is s e t (=1), crf b e co m e s an a g t co n t r o l r e g i s t er wi th crf:0-4 h o ldin g t h e a g t co ef f i cien t, crf:5 becom e s an a g t ena b le a nd crf:7 becom e s an a g t m u t e co n t r o l b i t. c o n t r o l b i t crf:5 co nn e c ts/ d is c o nn e c ts t h e a g t o u t p u t t o t h e s u mm er b l o c k a t t h e o u t p u t o f t h e d a c s e c t io n w h i l e con t r o l b i t crf:7 o v er r i des t h e ga in ta p s e t t in g wi th a m u t e , (zer o ga in) s e t t ing. t a b l e 10 sho w s t h e gain vs. dig i t a l s e t t ing fo r t h e a g t . i n th is ta b l e , a g t a n d d g t w e i g h t s a r e gi v e n f o r th e ca se o f vfbn x (co n n e c t e d t o t h e s i g m a-d e l t a m o d u l a to r s p o si t i ve in p u t) b e in g a t a hig h er p o t e n t i a l t h a n vfbpx (co n n e c t e d t o t h e sig m a- delt a m o d u l a t o r s n e g a t i ve in p u t). table 10. a n alog gain ta p se ttings a g t c 4 a g t c 3 a g t c 2 a g t c 1 a g t c 0 g a in ( d b ) 0 0 0 0 0 1 . 0 0 0 0 0 0 1 0 . 9 3 7 5 0 0 0 1 0 0 . 8 7 5 0 0 0 1 1 0 . 8 1 2 5 0 0 1 0 0 0 . 7 5 0 1 1 1 1 0 . 0 6 2 5 1 0 0 0 0 ? 0 . 0 6 2 5 1 1 1 0 1 ? 0 . 8 7 5 1 1 1 1 0 ? 0 . 9 3 7 5 1 1 1 1 1 ? 1 . 0 0
ad73322l rev. a | page 18 of 48 digital gain tap the digital gain tap features a programmable gain block whose input is taken from the bit stream output of the adcs sigma delta modulator. this single bit input (1 or 0) is used to add or subtract a programmable value, which is the digital gain tap setting, to the output of the dac sections interpolator. the programmable setting has 16-bit resolution and is programmed using the settings in control registers g and h, as shown in table 11. in this table, agt and dgt weights are given for the case of vfbnx (connected to the sigma-delta modulators positive input) being at a higher potential than vfbpx (connected to the sigma-delta modulators negative input). table 11. digital gain tap settings dgt15C0 (hex) gain 0x8000 ?1.00 0x9000 ?0.875 0xa000 ?0.75 0xc000 ?0.5 0xe000 ?0.25 0x0000 0.00 0x2000 +0.25 0x4000 +0.05 0x6000 +0.75 0x7fff +0.99999 serial port (sport) the codecs communicate with a host processor via the bidirectional synchronous serial port (sport), which is compatible with most modern dsps. the sport is used to transmit and receive digital data and control information. the dual codec is implemented using two separate codec blocks that are internally cascaded with serial port access to the input of codec 1 and the output of codec 2. this allows other single or dual codec devices to be cascaded together (up to a limit of eight codec units). in both transmit and receive modes, data is transferred at the serial clock (sclk) rate with the msb being transferred first. due to the fact that the sport of each codec block uses a common serial register for serial input and output, commun- ications between an ad73322l codec and a host processor (dsp engine) must always be initiated by the codecs themselves. in this configuration, the codecs are described as being in master mode. this ensures that there is no collision between input data and output samples. sport overview the ad73322l sport is a flexible, full-duplex, synchronous serial port having a protocol designed to allow up to four ad73322l devices (or combinations of ad73322l dual codecs and ad73311 single codecs up to eight codec blocks) to be connected, in cascade, to a single dsp via a 6-wire interface. it has a very flexible architecture that can be configured by programming two of the internal control registers in each codec block. the device has three distinct modes of operation: control mode, data mode, and mixed control/data mode. note that because each codec has its own sport section, the register settings in both sports must be programmed. the registers that control sport and sample rate operation (cra and crb) must be programmed with the same values, otherwise incorrect operation may occur. in control mode (cra:0 = 0), the devices internal configuration can be programmed by writing to the eight internal control registers. in this mode, control information can be written to or read from the codec. in data mode (cra:0 = 1), (cra:1 = 0), information sent to the device is used to update the decoder section (dac), while the encoder section (adc) data is read from the device. in this mode, only dac and adc data are written to or read from the device. mixed mode (cra:0 = 1 and cra:1 = 1) allows the user to choose whether the infor- mation being sent to the device contains control information or dac data. this is achieved by using the msb of the 16-bit frame as a flag bit. mixed mode reduces the resolution to 15 bits with the msb being used to indicate whether the information in the 16-bit frame is control information or dac/adc data. the sport features a single 16-bit serial register that is used for both input and output data transfers. as the input and output data must share the same register, some precautions must be observed. the primary precaution is that no informa- tion must be written to the sport without reference to an output sample event, which is when the serial register is overwritten with the latest adc sample word. once the sport starts to output the latest adc word, it is safe for the dsp to write new control or data-words to the codec. in certain con- figurations, data can be written to the device to coincide with the output sample being shifted out of the serial register see the interfacing section. the serial clock rate (crb:2C3) defines how many 16-bit words can be written to a device before the next output sample event happens.
ad73322l rev. a | page 19 of 48 the sport block diagram shown in figure 19 details the blocks associated with codecs 1 and 2, including the eight control registers (aCh), external mclk to internal dmclk divider, and serial clock divider. the divider rates are controlled by the setting of control register b. the ad73322l features a master clock divider that allows users the flexibility of dividing externally available high frequency dsp or cpu clocks to generate a lower frequency master clock internally in the codec, which may be more suitable for either serial transfer or sampling rate requirements. the master clock divider has five divider options (1 default condition, 2, 3, 4, 5) that are set by loading the master clock divider field in register b with the appropriate code (see ). once the internal device master clock (dmclk) has been set using the master clock divider, the sample rate and serial clock settings are derived from dmclk. the sport can work at four different serial clock (sclk) rates chosen from dmclk, dmclk/2, dmclk/4, or dmclk/8, where dmclk is the internal or device master clock resulting from the external or pin master clock being divided by the master clock divider. sport register maps there are two register banks for each codec in the ad73322l, the control register bank and the data register bank. the control register bank consists of eight read/write registers, each eight bits wide. table 16 shows the control register map for the ad73322l. the first two control registers, cra and crb, are reserved for controlling the sport. they hold settings for parameters such as serial clock rate, internal master clock rate, sample rate and device count. as both codecs are internally cascaded, registers cra and crb on each codec must be programmed with the same setting to ensure correct operation (this is shown in the programming examples). the other five registers, crc through crh, are used to hold control settings for the adc, dac, reference, power control, and gain tap sections of the device. it is not necessary for the contents of crc through crh on each codec be similar. control registers are written to on the negative edge of sclk. the data register bank consists of two, 16-bit registers that are the dac and adc registers. master clock divider the ad73322l features a programmable master clock divider that allows the user to reduce an externally available master clock, at pin mclk, by a ratio of 1, 2, 3, 4, or 5 to produce an internal master clock signal (dmclk) that is used to calculate the sampling and serial clock rates. the master clock divider is programmable by setting crb:4-6. table 12 shows the division ratio corresponding to the various bit settings. the default divider ratio is divide-by-one. table 12. dmclk (internal) rate divider settings mcd2 mcd1 mcd0 dmclk rate 0 0 0 mclk 0 0 1 mclk/2 0 1 0 mclk/3 0 1 1 mclk/4 1 0 0 mclk/5 1 0 1 mclk 1 1 0 mclk 1 1 1 mclk serial clock rate divider the ad73322l features a programmable serial clock divider that allows users to match the serial clock (sclk) rate of the data to that of the dsp engine or host processor. the maximum sclk rate available is dmclk, and the other available rates are dmclk/2, dmclk/4, and dmclk/8. the slowest rate (dmclk/8) is the default sclk rate. the serial clock divider is programmable by setting bits crb:2C3. table 13 shows the serial clock rate corresponding to the various bit settings. table 13. sclk rate divider settings scd1 scd0 sclk rate 0 0 dmclk/8 0 1 dmclk/4 1 0 dmclk/2 1 1 dmclk sample rate divider the ad73322l features a programmable sample rate divider that allows users flexibility in matching the codecs adc and dac sample rates (decimation/interpolation rates) to the needs of the dsp software. the maximum sample rate available is dmclk/256, which offers the lowest conversion group delay, while the other available rates are dmclk/512, dmclk/1024, and dmclk/2048. the slowest rate (dmclk/2048) is the default sample rate. the sample rate divider is programmable by setting bits crb:0-1. table 14 shows the sample rate corresponding to the various bit settings. table 14. sample rate divider settings dir1 dir0 sclk rate 0 0 dmclk/2048 0 1 dmclk/1024 1 0 dmclk/512 1 1 dmclk/256
ad73322l rev. a | page 20 of 48 dac advance register the loading of the dac is internally synchronized with the unloading of the adc data in each sampling interval. the default dac load event happens one sclk cycle before the sdofs flag is raised by the adc data being ready. however, this dac load position can be advanced before this time by modifying the contents of the dac advance field in control register e (cre:0C4). the field is five bits wide, allowing 31 increments of weight 1/(f s 32), as shown in table 15. the sample rate, f s, depends on the setting of both the mclk divider and the sample rate divider, as shown in table 12 and table 14. in certain circumstances this dac update adjustment can reduce the group delay when the adc and dac are used to process data in series. for more information about how the dac advance register can be used, see the section configuring an ad73322l to operate in mixed mode. note: the dac advance register should not be changed while the dac section is powered up. table 15. dac timing control da4 da3 da2 da1 da0 time advance 0 0 0 0 0 0 s 0 0 0 0 1 1/(f s 32) s 0 0 0 1 0 2/(f s 32) s 1 1 1 1 0 30/(f s 32) s 1 1 1 1 1 31/(f s 32) s table 16. control register map address (binary) name description type width reset setting (hex) 000 cra control register a r/ w 8 0x00 001 crb control register b r/ w 8 0x00 010 crc control register c r/ w 8 0x00 011 crd control register d r/ w 8 0x00 100 cre control register e r/ w 8 0x00 101 crf control register f r/ w 8 0x00 110 crg control register g r/ w 8 0x00 111 crh control register h r/ w 8 0x00 table 17. control word description 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 c/ d r/ w device address register address register data control frame description bit 15 control/ data when set high, this bit signifies a control word in program or mixed program/data modes. when set low, it signifies a data-word in mixed program/data mode or an invalid control word in program mode. bit 14 read/ write when set low, this bit tells the device that the data fi eld is to be written to the register selected by the register field setting, provided the address field is zero. when set high, it tells the device that the selected register is to be written to the data field in the input serial register and that the new control word is to be output from the device via the serial output. bits 13 to 11 device address this 3-bit field holds the address information. only wh en this field is zero is a device selected. if the address is not zero, it is decremented and the contro l word is passed out of the device via the serial output. bits 10 to 8 register address this 3-bit field is used to select one of the eight control registers on the ad73322l. bits 7 to 0 register data this 8-bit field holds the data that is to be written to or read from the selected register provided the address field is zero.
ad73322l rev. a | page 21 of 48 control register a table 18. control register a description 7 6 5 4 3 2 1 0 reset dc2 dc1 dc0 slb blb mm data/ pgm bit name description 0 data/ pgm operating mode (0 = program; 1 = data mode) 1 mm mixed mode (0 = off; 1 = enabled) 2 dlb digital loop-back mode (0 = off; 1 = enabled) 3 slb sport loop-back mode (0 = off; 1 = enabled) 4 dc0 device count (bit 0) 5 dc1 device count (bit 1) 6 dc2 device count (bit 2) 7 reset software reset (0 = off; 1 = initiates reset) control register b table 19. control register b description 7 6 5 4 3 2 1 0 cee mcd2 mcd1 mcd0 scd1 scd0 dir1 dir0 bit name description 0 dir0 decimation/interpolation rate (bit 0) 1 dir1 decimation/interpolation rate (bit 1) 2 scd0 serial clock divider (bit 0) 3 scd1 serial clock divider (bit 1) 4 mcd0 master clock divider (bit 0) 5 mcd1 master clock divider (bit 1) 6 mcd2 master clock divider (bit 2) 7 cee control echo enable (0 = off; 1 = enabled) control register c table 20. control register c description 7 6 5 4 3 2 1 0 ru puref pudac puadc puia puagt pu bit name description 0 pu power-up device (0 = power-down; 1 = power on) 1 puagt analog gain tap power (0 = power-down; 1 = power on) 2 puia input amplifier power (0 = power-down; 1 = power on) 3 puadc adc power (0 = power-down; 1 = power on) 4 pudac dac power (0 = power-down; 1 = power on) 5 puref ref power (0 = power-down; 1 = power on) 6 ru refout use (0 = disable refout; 1 = enable refout) 7 reserved, must be programmed to 0
ad73322l rev. a | page 22 of 48 control register d table 21. control register d description 7 6 5 4 3 2 1 0 mute ogs2 ogs1 ogs0 rmod igs2 igs1 igs0 bit name description 0 igs0 input gain select (bit 0) 1 igs1 input gain select (bit 1) 2 igs2 input gain select (bit 2) 3 rmod reset adc modulator (0 = off; 1 = reset enabled) 4 ogs0 output gain select (bit 0) 5 ogs1 output gain select (bit 1) 6 ogs2 output gain select (bit 2) 7 mute output mute (0 = mute off; 1 = mute enabled) control register e table 22. control register e description 7 6 5 4 3 2 1 0 dgte ibyp da4 da3 da2 da1 da0 bit name description 0 da0 dac advance setting (bit 0) 1 da1 dac advance setting (bit 1) 2 da2 dac advance setting (bit 2) 3 da3 dac advance setting (bit 3) 4 da4 dac advance setting (bit 4) 5 ibyp interpolator bypass (0 = bypass disabled; 1 = bypass enabled) 6 dgte digital gain tap enable (0 = disabled; 1 = enabled) 7 reserved (program to 0) control register f table 23. control register f description 7 6 5 4 3 2 1 0 alb/agtm inv seen/agte agtc4 agtc3 agtc2 agtc1 agtc0 bit name description 0 agtc0 analog gain tap coefficient (bit 0) 1 agtc1 analog gain tap coefficient (bit 1) 2 agtc2 analog gain tap coefficient (bit 2) 3 agtc3 analog gain tap coefficient (bit 3) 4 agtc4 analog gain tap coefficient (bit 4) 5 seen/ single-ended enable (0 = disabled; 1 = enabled) agte analog gain tap enable (0 = disabled; 1 = enabled) 6 inv input invert (0 = disabled; 1 = enabled) 7 alb/ analog loopback of output to input (0 = disabled; 1 = enabled) agtm analog gain tap mute (0 = off; 1 = muted)
ad73322l rev. a | page 23 of 48 control register g table 24. control register g description 7 6 5 4 3 2 1 0 dgtc7 dgtc6 dgtc5 dgtc4 dgtc3 dgtc2 dgtc1 dgtc0 bit name description 0 dgtc0 digital gain tap coefficient (bit 0) 1 dgtc1 digital gain tap coefficient (bit 1) 2 dgtc2 digital gain tap coefficient (bit 2) 3 dgtc3 digital gain tap coefficient (bit 3) 4 dgtc4 digital gain tap coefficient (bit 4) 5 dgtc5 digital gain tap coefficient (bit 5) 6 dgtc6 digital gain tap coefficient (bit 6) 7 dgtc7 digital gain tap coefficient (bit 7) control register h table 25. control register h description 7 6 5 4 3 2 1 0 dgtc15 dgtc14 dgtc13 dgtc12 dgtc11 dgtc10 dgtc9 dgtc8 bit name description 0 dgtc8 digital gain tap coefficient (bit 8) 1 dgtc9 digital gain tap coefficient (bit 9) 2 dgtc10 digital gain tap coefficient (bit 10) 3 dgtc11 digital gain tap coefficient (bit 11) 4 dgtc12 digital gain tap coefficient (bit 12) 5 dgtc13 digital gain tap coefficient (bit 13) 6 dgtc14 digital gain tap coefficient (bit 14) 7 dgtc15 digital gain tap coefficient (bit 15)
ad73322l rev. a | page 24 of 48 ope ra tion reset t ing the ad73322l the res e t pi n re s e t s a l l t h e c o n t ro l re g i ste r s . a l l re g i ste r s are r e s e t to z e r o , i ndic a t i n g t h a t t h e defa u l t scl k r a te (d mclk /8 ) a nd s a m p le r a t e (d m c lk/2048 ) a r e a t a minim u m t o en sur e t h a t s l o w sp e e d ds p en g i n e s can co mm uni c a t e ef fe c t i v e l y . a s wel l a s re s e tt i n g t h e c o n t ro l re g i ste r s u s i n g t h e res e t pi n , t h e de vice can b e r e s e t usin g t h e re s e t b i t (cr a :7 ) in c o n t r o l r e g i s t e r a . b o t h h a rdw a re a n d s o f t w a re re s e t s r e qu i r e f o u r d m clk c y c l es. on r e s e t, d a t a / pgm (cra:0) is set t o 0 (defa u l t condi t i o n ) t h us ena b l i n g p r o g r a m m o de. t h e r e s e t co ndi t i on s en su r e t h a t t h e de vic e m u st b e p r o g r a mme d to t h e c o rr ect se t t i n g s a f t e r po w e r - u p o r r e se t . f o ll o w in g a r e set , t h e s d o f s is as s e r t ed 2048 d m cl k c y c l es a f t e r res e t going hi g h . the da t a t h a t is o u t p ut fol l o w ing r e s e t an d d u r i n g p r og ra m m o de is r a n d om an d con t ain s n o va l i d info r m a t io n u n t i l e i t h e r d a t a o r m i xe d m o de is s e t. po wer mana geme nt the individ u al f u n c tio n al b l o c ks o f th e ad7332 2l ca n be en a b led sep a ra te l y b y p r ogra mmin g t h e p o w e r c o n t r o l regis t er cr c. i t al lo ws c e r t a i n s e c t io n s to be p o w e r e d do wn if n o t r e q u ir e d , w h ich adds t o t h e de v i ce s f l exi b i l i t y i n t h a t t h e us er ne e d not i n c u r t h e p e n a lt y of h a v i ng to pro v i d e p o we r for a cer t a i n s e c t io n i f i t is n o t n e cess a r y to t h e desig n . t h e p o w e r c o n t ro l re g i ste r s pro v i d e i n d i v i du a l c o n t ro l s e tt i n g s f o r t h e ma j o r f u n c t i o n a l b l o c ks o n e a ch co de c un i t an d a l s o a g l ob a l o v er r i de tha t al l o ws al l s e c t io n s t o be p o w e r e d u p b y s e t t in g t h e b i t. u s in g this m e tho d t h e us er co u l d , f o r exa m p l e , individ u a l l y ena b le a cer t a i n s e c t io n, such as t h e r e fer e nce ( c rc:5), an d d i sa b l e all o t h e r s . th e glo b al po w e r - u p (cr c :0) ca n be use d t o ena b le a l l s e c t ion s , b u t if p o w e r - do w n is r e q u ire d usin g t h e g l ob al co n t r o l , t h e r e fer e n c e is st i l l ena b le d , i n t h is cas e , b e ca us e i t s i ndivi d u a l b i t is s e t. refer to t a b l e 21 fo r det a i l s o f t h e se t t i n g s o f c r c. n o te: a s b o t h co de c un i t s shar e a co m m o n r e fer e n c e, t h e re f e re nc e c o n t r o l bit s ( c rc : 5 - 7 ) i n e a c h sp o r t are w i re - o r e d t o al lo w ei t h er de vice t o co n t r o l t h e r e fer e n c e . oper a t ing modes ther e a r e t h r e e ma in m o des o f o p era t ion a v a i l a b l e o n t h e ad73322l: p r og ra m, da t a , an d mixed p r og ra m/da t a m o des. t w o ot he r op e r a t i n g m o d e s are t y pi c a l l y re s e r v e d a s d i ag - n o st ic m o des: d i g i t a l and s p or t lo o p -b ack. the de vic e co nf igur a t io n r e g i ster s e t t i n gs ca n b e chan ge d o n ly in p r o g r a m a n d m i xe d p r o g r a m/ d a t a m o des. i n a l l m o des, t r ans f e r s of i n f o r m a t i o n to or f r om t h e d e v i c e o c c u r i n 1 6 - bit p a ck ets; t h er efo r e t h e ds p en g i n e s s p o r t is pr og ra mm e d fo r 16-b i t tra n sfers. progr a m ( c ontrol ) mode i n p r og ra m m o de , cr a : 0 = 0, t h e us er wr i t es to t h e con t r o l r e g i sters to s e t up t h e de vic e fo r desir e d o p er a t ions p or t o p era t ion, cas c ade len g t h , p o w e r ma na g e m e n t , in p u t/o u t p ut ga in, e t c. i n t h is m o de , t h e 16 -b i t info r m a t ion p a ck et s e n t t o t h e d e v i c e b y t h e d s p e n g i ne i s i n t e r p re te d a s a c o n t ro l word w h o s e fo r m a t is sh o w n in t a b l e 17. i n t h is m o de , t h e us er m u st addr ess t h e d e v i ce to b e p r o g r a mm e d usin g t h e addr ess f i eld of t h e co n t r o l w o r d . this f i e l d is re ad b y t h e d e vic e a nd if i t is zer o (000 b i n), t h e device r e cog n izes th e w o r d as b e in g addr es s e d t o i t . i f t h e ad dr ess f i eld is n o t zer o , i t is t h e n de cr e m e n te d an d t h e c o n t ro l word i s p a ss e d out of t h e d e v i c e e it h e r to t h e ne x t de vice in a cas c ade o r b a ck t o t h e ds p en g i ne . this 3- b i t addr es s fo r m a t al lo ws t h e us er t o uni q ue l y addr es s a n y o n e o f u p t o eig h t de v i ces i n a cas c ade; ple a s e n o t e t h a t t h is addr essi n g s c h e m e is va li d o n ly in s e ndi n g co n t r o l info r m a t io n to t h e de vi ce a dif f er en t fo r m a t is us e d to s e nd d a c d a t a to th e de vice(s). a s th e ad73322l is a d u al co dec, i t f e a t ur es tw o s e p a r a te de vic e addr ess e s fo r pr o g r a m m i ng pu r p o s e s . i f t h e ad73322l is us ed in a standalon e co nf igur a t ion co nn ec t e d t o a ds p , t h e tw o de vice addr es s e s co r r es p o n d t o 0 a nd 1. i f t h e ad73322l is conf igur ed in a cas c ade o f m u l t i p le , d u al , o r sin g le co decs (ad73322l o r ad73311), i t s de vice addr es s e s c o rr e s po n d wi th i t s h a r d w i r e d pos i ti o n in th e c a sc ad e . f o l l o w in g r e s e t, w h en t h e s e p i n is ena b le d , t h e co de c r e s p on ds b y r a isin g t h e sd of s p i n to i ndic a te t h a t an ou t p ut s a m p le e v en t has o c c u r r e d . c o n t r o l w o r d s ca n b e wr i t ten to t h e de vic e t o c o i n ci d e w i th t h e d a ta be i n g s e n t o u t o f th e s p o r t , a s s h o w n i n fi g u re 2 0 , or t h e y c a n l a g t h e output word s by a t i me i n te r v a l t h a t sh o u l d n o t exce e d t h e s a m p le in t e r v a l . af ter r e s e t, o u t p u t f r a m e sy n c p u ls es o c c u r a t a s l o w er defa u l t s a m p le ra t e , w h ich is d m clk/2048, un til c o n t r o l reg i s t er b is p r og ra mm e d , a f t e r w h ich t h e s d ofs p u ls es a r e s e t acco r d i n g t o t h e con t e n ts o f d i r 0 - 1 . t h i s all o w s s l o w co n t r o ll e r d evi ce s t o es ta b l is h co mm unic a t io n wi th t h e ad73 322l. dur i n g p r og ra m m o de , th e da t a o u t p u t b y t h e de vice is ra n d om an d sho u ld n o t b e i n te r p re te d a s a d c da t a . sample word (device 2) se sdofs sclk sdo sdifs sdi sample word (device 1) control word (device 2) control word (device 1) 00691-020 f i gure 20. inte r f ace sign al t i m i ng fo r control mod e o p e r atio n
ad73322l rev. a | page 25 of 48 da t a m o d e on ce t h e de vice has been co nf ig ur ed b y p r og ra mming t h e co r r e c t s e t t in gs t o t h e va r i o u s c o n t r o l r e g i s t ers, t h e de vic e ma y ex i t p r o g ra m m o d e an d e n ter d a t a mo de. this is don e b y p r o g ra mming t h e d a t a / pgm (cra:0) b i t t o a 1 a nd mm (cr a :1) t o 0. on ce t h e de v i ce is in da t a mo de , t h e 16 -b i t in p u t da t a f r a m e is in t e r p r e t e d as d a c d a t a ra t h er t h an a co n t r o l f r a m e . this da t a is t h erefo r e lo ade d dire c t l y t o t h e d a c r e g i s t er . a s f i gu r e 20 s h o w s, b e c a us e t h e e n t i r e i n p u t da t a f r a m e co n t a i n s d a c da ta i n da ta m o de , t h e de vi ce r e lies o n co un t i n g th e n u m b er o f in p u t f r am e sy n c s r e cei v ed a t t h e s d ifs p i n. w h en t h a t n u m b er e q uals t h e de v i ce co u n t st o r e d i n t h e de vice co un t f i e l d o f c r a, t h e de vice kn o w s t h a t t h e p r es en t da t a f r a m e b e in g r e c e i v e d is i t s o w n d a c u p da te da t a . w h en t h e de vice is in n o r m a l da t a m o d e (t ha t is, m i xe d m o de dis a b l e d ), i t m u st re c e ive a h a rdw a re re s e t to re pro g r a m an y of t h e c o n t ro l re g i ste r s e tt i n g s . i n a s i n g le ad7 3322l co nf igura t io n, eac h 16 -b i t da ta f r a m e s e n t f r om t h e d s p to t h e d e v i c e i s i n te r p re te d a s d a c da t a , b u t i t i s n e c e s s a r y t o se n d tw o d a c w o r d s pe r sa m p l e pe ri o d in o r der to en sur e t h e d a c up da te. als o , a s t h e d e v i ce co u n t s e t t in g defa u l ts t o 1, i t m u st b e s e t t o 2 (001b) to en s u r e co r r ec t u p da te o f bo t h d a cs o n t h e ad73322l. the s e c t io n d a c t i min g c o n t rol e x a m ple det a i l s t h e ini t i a l- iza t io n and o p era t io n o f a n ad73322l in n o r m al da t a m o de . se sdofs sclk sdo sdifs sdi adc sample word (device 2) adc sample word (device 1) dac data word (device 2) dac data word (device 1) 00691-021 f i g u re 21. inte r f ace sig n al ti m i ng f o r d a t a m o d e o p e r at i o n mixed progr a m/d a t a mode this m o de al lo ws t h e us er t o s e nd co n t r o l w o r d s t o t h e de v i ce a l o n g w i th th e d a c d a t a . t h i s pe rm i t s a d a p ti v e c o n t r o l o f t h e de vice w h er e con t r o l o f t h e i n pu t/o u t p u t gain s, et c., can b e a f f e ct ed b y in t e rl ea v i n g co n t r o l w o r d s al o n g wi t h t h e n o rm al f l o w o f d a c d a t a . t h e st anda rd da t a f r a m e r e ma in s 16 b i ts , b u t t h e m s b is us e d as a f l a g b i t t o i ndic a t e w h et h e r t h e r e mainin g 15 b i ts o f t h e f r am e r e p r es e n t d a c da t a o r co n t r o l info r m a t io n. i n th e c a s e o f d a c d a ta , th e 1 5 b i t s a r e l o a d e d w i t h m s b j u st if i c a t ion and ls b s e t to 0 to t h e d a c r e g i ster . mixe d mo de is ena b le d b y s e t t i n g t h e mm b i t (cr a :1) t o 1 and t h e da t a / pgm b i t (cr a :0) t o 1. i n t h e case wher e co n t r o l set t in g ch ange s are re qu i r e d du r i ng no r m a l op e r a t i o n , t h i s m o d e al lo ws t h e ab il i t y t o lo ad bo th c o n t r o l a n d da t a inf o r m a t io n w i th t h e s l i g h t in co n v e n i e n c e o f f o rm a t ti n g t h e da ta . n o t e th a t th e o u t p u t sa m p le s f r o m th e ad c will also h a v e th e ms b s e t t o z e ro to i n d i c a te i t i s a d a t a - w ord. the s e c t io n c o nf igur in g a n ad73322l t o o p era t e in m i xed m o de deta ils t h e ini t ializa t i o n and o p era t io n o f a n ad73322 l o p e r a t in g in m i x e d m o d e . n o t e th a t i t i s n o t e s s e n t i a l t o loa d t h e c o n t ro l re g i ste r s i n pro g r a m m o d e b e f o re s e tt i n g m i x e d m o de ac t i v e . i t is als o p o s s i b le to ini t ia t e mixed m o de b y p r o g r a m m i n g c r a w i th th e fi r s t c o n t r o l w o r d a n d th e n i n t e r l ea vi n g co n t r o l w o r d s w i t h d a c d a ta . digit a l l o op -ba c k m o de this m o d e can b e us e d fo r di a g n o st ic p u r p o s es , a l lo w i n g t h e us er t o fe e d t h e ad c s a m p les f r o m t h e ad c r e g i s t er dir e c t l y to t h e d a c r e g i st e r . this fo r m s a lo o p -b ack o f t h e a n a l og in p u t t o th e a n alog o u t p u t b y r e co n s tr ucti n g t h e en coded si gn al usi n g t h e de co der channel. the s e r i a l in ter f ace co n t i n ues to w o rk, w h ich a l lo ws t h e us er t o co n t r o l ga in s e t t in gs, s c lk f r e q uen c y , s a m p le ra te , et c . onl y w h en d l b is ena b le d w i t h mixe d mo de o p era t ion can t h e us er dis a b l e t h e d l bot her w is e t h e de vice mu s t b e r e s e t . sport l oop -ba c k mode this m o de al lo ws t h e us er t o ver i f y t h e ds p in t e r f acin g and co nn e c t i o n b y wr i t in g w o r d s to t h e s p or t o f t h e de vi ces an d ha v e t h em r e t u r n e d back u n c h an g e d a f t e r a del a y o f 16 sclk c y cles. th e f r a m e sy n c and da t a -w o r d t h a t a r e s e n t t o t h e de v i ce a r e r e t u r n e d v i a t h e o u t p u t p o r t . a g a i n, slb m o de can o n ly b e dis a b l e d w h e n us e d i n co n j u n c t io n wi t h m i xe d m o de, o t h e r w i s e th e de vice m u st be r e s e t.
ad73322l rev. a | page 26 of 48 anal og l o op -ba c k m o de i n a n alog lo o p - b ack m o de , t h e dif f er en t i al d a c o u t p ut is co nn e c t e d, v i a a lo o p -b ack s w i t ch, t o t h e a d c in p u t, as sho w n in f i gur e 22. this m o de al lo ws t h e ad c c h a n nel t o c h eck f u nc t i on a l it y of t h e d a c ch a n n e l a s t h e re c o ns t r u c te d output sig n a l can b e mo ni to r e d usin g t h e ad c as a s a m p ler . a n a l o g lo o p -b ack is e n a b le d b y s e t t i n g t h e alb b i t (c r f :7). n o t e t h a t a n a l og lo o p -b ack ca n o n ly b e enab le d if t h e ana l og ga i n t a p is p o wer e d do w n (crc:1 = 0). 00691-022 inverting op amps analog gain tap powered down analog loop-back select invert single- ended enable continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/ ?15db pga 0/38db pga gain 1 refout refcap reference v ref f i g u re 22. a n a l og l oop -b ack conn ec t i v i t y
ad73322l rev. a | page 27 of 48 interf acing the ad73322 l ca n be in t e r f ace d t o m o s t m o der n ds p en g i n e s usin g co n v e n t i ona l s e r i a l p o r t c o nn e c t i o n s an d a n ext r a enab le co n t r o l line. b o t h s e r i a l i n p u t and o u tp u t d a t a us e a n accom- p a n y i n g f r a m e s y n c hr o n iz a t io n sig n a l t h a t is ac t i v e hig h on e clo c k c y cle b e fo r e t h e s t a r t o f t h e 16-b i t w o r d o r d u r i n g t h e last b i t o f t h e p r e v i ous w o r d if tra n smis sio n is con t in uo us. th e s e r i al c l o c k (sc l k) is a n o u t p u t f r o m th e co de c a nd is us ed to def i ne t h e s e r i a l t r a n sfer r a te to t h e ds p s tx a nd rx p o r t s. t w o p r ima r y co nf igura t io n s c a n b e us e d : t h e f i rst is sh o w n in f i gur e 22 w h er e t h e ds p s tx da t a , tx f r a m e sy nc, rx da t a , an d rx f r a m e sy n c ar e co nn ec t e d t o th e co dec s s d i, s d ifs, s d o , a nd s d of s, r e sp e c t i vely . thi s c o nf igur a t io n, r e fer r e d to as indir e c t ly co u p l e d o r n o nf r a m e sy n c lo o p - b ack, has t h e ef fe c t o f d e c o upl i n g t h e t r ans m i s s i on of i n put d a t a f r om t h e re c e ipt of o u t p ut da t a . t h e del a y b e tw e e n r e cei p t o f co de c o u t p u t d a t a and t r a n smissio n o f in p u t da t a fo r t h e co de c is d e t e r m ine d b y t h e ds p s s o f t wa r e l a t e n c y . w h en p r og ra m m in g t h e ds p s e r i a l p o r t fo r t h is co nf igura t io n, i t is n e cess a r y to s e t t h e rx fs as a n i n p u t and t h e tx fs as a n o u t p ut gener a te d b y t h e ds p . t h is co nf igur a t ion is m o st us ef u l w h en op era t i n g in mixe d m o de, as t h e ds p has t h e a b i l i t y t o de cide ho w man y w o r d s (ei t h e r d a c o r co n t r o l) ca n b e s e n t to th e co decs. this m e an s tha t f u l l co n t r o l ca n be im p l em en t e d o v er t h e de vi ce co nf igur a t io n a s w e l l as u p d a t i n g t h e d a c i n a gi v e n sa m p l e in t e r v al . the s e cond co n f igur a t io n (sh o w n i n f i gur e 24 ) has t h e ds p s tx d a t a an d rx d a t a conne c t e d to t h e co de c s sdi a nd s d o , r e s p e c t i ve l y , w h i l e t h e ds p s tx a nd rx f r a m e sy n c s a r e co nn e c te d to t h e co de c s s d if s a nd s d of s. i n t h is co nf igur a t io n, refer r e d to as dir e c t ly co u p le d o r f r a m e sy n c lo o p -bac k, t h e f r a m e sy n c sig n a l s a r e co nn e c t e d t o g e th er and th e i n p u t da ta t o th e co d e c i s f o r c ed t o b e syn c h r o n o u s wi t h t h e o u t p u t da t a f r o m t h e co dec. the ds p m u st b e p r og ra mm ed s o tha t bo t h t h e tx fs a n d rx fs a r e in p u ts as t h e co dec s d o f s is in p u t t o b o t h . t h is co nf igura t ion gua r an t e es t h a t i n p u t and o u t p u t ev en t s o c cur s i m u l t a n eo us l y a n d i s t h e s i m p l e s t co nf igura t io n fo r o p era t io n in no r m a l d a t a m o d e . w h e n p r og ra mmin g t h e ds p i n t h is c o nf igura t io n, i t is ad vis a b l e t o p r e l oa d th e t x r e gi s t e r w i th th e fi r s t c o n t r o l w o r d t o b e s e n t be f o r e th e cod e c i s tak e n o u t o f r e se t . t h is e n s u r e s th a t th i s w o r d is tra n smi t t e d t o co in cide wi th t h e f i rs t o u t p u t w o r d f r o m th e de vice(s). tfs dt sclk dr rfs adsp-21xx dsp ad73322l codec codec1 codec2 sdifs sdi sclk sdo sdofs 00691-023 f i gur e 2 3 . indir ectly c o uple d o r no nfr a me s y nc l oop -ba c k co nf ig u r at i o n c a sc ade oper a t ion the ad73322 l has been desig n ed t o s u p p o r t cas c adin g o f co decs f r o m a sin g le ds p s e r i al p o r t (s ee f i gur e 36). cas c ade d o p er a t ion can su p p o r t mixes o f d u a l - o r sin g le - c ha nnel de vices wi t h t h e maxi m u m n u m b er o f c o de c uni t s b e ing eig h t (t he ad73322l is eq ui valen t t o tw o co dec uni t s). th e s p or t in t e r f ace p r o t o c ol has b e en desi g n e d s o t h a t de vice addr es sin g is b u i l t in t o t h e p a ck et o f info r m a t io n s e n t t o t h e de vic e . this al lo ws t h e cas c ade t o b e fo r m e d wi t h n o ext r a ha r d wa r e o v erhe ad fo r co n t r o l sig n als o r addr es sin g . a c a s c ade can be f o r m ed in ei t h er o f th e tw o mo des p r e v io us l y dis c us s e d . ther e ma y b e s o m e r e s t r i c t io ns in cas c ade op e r a t io n d u e t o t h e n u m b er o f de vi ces co nf igur e d i n t h e cas c ade and t h e s a m p lin g ra t e an d s e r i a l clo c k ra t e ch os e n . the fol l o w ing r e la t i o n shi p det a i l s t h e r e st r i c t io n s i n co nf ig ur in g a co de c c a s c ad e . n u m b e r o f c ode s w o r d si z e (1 6) sa m p l i n g ra t e se ri a l cl o c k ra t e 00691-024 tfs dt sclk dr rfs adsp-21xx dsp ad73322l codec codec1 codec2 sdifs sdi sclk sdo sdofs f i g u re 24. d i r e c t ly coupl e d or f r a m e sy nc l oop -b ack co nf ig ur at ion w h en usi n g t h e indir e c t ly co u p le d f r a m e sy n c c o nf igur a t io n in ca s c a d e d o p e r a t io n, b e a w a r e o f t h e r e st r i c t ion s in s e n d in g da ta t o all d e v i ce s i n t h e ca s c a d e . ef f e cti v e l y th e tim e allo w e d is g i ven b y t h e s a m p lin g in ter v a l (m/d mclk w her e m can b e 256, 512, 1024, o r 2048), whic h is 125 s f o r a sa m p le ra te o f 8 kh z. i n this in t e r v al , t h e ds p m u s t tra n sf er n 16 b i ts o f info r m a t io n w h er e n is t h e n u m b er o f de vi ces in t h e cas c ade .
ad73322l rev. a | page 28 of 48 each bit will take 1/sclk and, allowing for any latency between the receipt of the rx interrupt and the transmission of the tx data, the relationship for successful operation is given by m/dmclk > (( n 16/ sclk ) + t interrupt latency ) the interrupt latency will include the time between the adc sampling event and the rx interrupt being generated in the dspthis should be 16 sclk cycles. because the ad73322l is configured in cascade mode, each device must know the number of devices in the cascade because the data and mixed modes use a method of counting input frame sync pulses to decide when they should update the dac register from the serial input register. control register a contains a 3-bit field (dc0-2) that is programmed by the dsp during the programming phase. the default condition is that the field contains 000b, which is equivalent to a single device in the cascade (see table 26). however, for cascade operation this field must contain a binary value that is one less than the number of devices in the cascade, which is 001b for a single ad73322l device configuration. table 26. device count settings dc2 dc1 dc0 cascade length 0 0 0 1 0 0 1 2 0 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8
ad73322l rev. a | page 29 of 48 perf orm ance b e ca us e t h e ad73322l is desig n e d t o p r o v ide hig h p e r f o r - ma n c e an d lo w cos t co n v ersion, i t is im p o r t a n t to un derstan d h o w hig h p e r f o r ma n c e ca n b e achie v e d i n a ty p i ca l a p plic a t ion. b y m e a n s o f spe c tral gra p h s , th is secti o n o u tlin e s th e t y p i cal p e r f or m a nc e of t h e d e v i c e a n d h i g h l i g h t s s o me of t h e opt i ons a v a i la b l e t o us ers in achie v i n g t h eir desir e d s a m p le ra te , ei t h e r dire c t ly i n t h e d e v i c e or b y doing s o me p o st-p ro c e ss ing in t h e ds p , w h i l e als o s h o w in g t h e adva n t a g es an d di s a d v an t a g e s o f t h e dif f er en t a p p r o a ch es. enc o der sec t ion the ad73322 l o f f e rs a va r i a b le s a m p lin g r a t e f r o m a f i xed m c lk f r eq uenc ywi th 64 kh z, 32 kh z, 16 kh z, and 8 kh z bein g a v a i la b l e wi th a 16.384 m h z ext e r n al c l o c k. e a c h o f t h es e s a m p lin g ra t e s p r es er v e s t h e s a me s a m p l i n g ra t e in t h e ad c s sig m a-de l t a m o d u la t o r , which en s u r e s t h a t t h e n o is e p e r f o r ma n c e is o p t i mize d i n e a ch cas e . th e exa m ples t h a t f o l l ow s h ow t h e p e r f o r m a n c e o f a 1 k h z s i n e w a v e w h e n c o n v e r te d a t t h e v a r i ou s s a m p l e r a te s . the ra n g e o f s a m p lin g r a t e s is a i m e d t o o f fer t h e us er a deg r e e o f f l ex i b i l i t y in de cid i n g h o w t h e a n a l o g f r o n t end is to b e im p l em en t e d . th e hig h s a m p le ra t e s o f 64 kh z a nd 32 kh z a r e su i t e d to t h o s e a p pl ic a t ions , su ch as ac t i v e c o n t rol, w h e r e l o w co n v ersio n g r o u p dela y is es s e n t ial . o n t h e ot h e r ha n d , t h e lo w e r s a m p le ra t e s o f 16 khz and 8 k h z a r e b e t t er sui t e d fo r a p plic a t io n s s u ch as te leph on y , w h er e t h e lo w e r s a m p le ra t e s re su lt i n l o w e r d s p o v e r he a d . f i gur e 29 sh o w s th e s p ectr um o f th e 1 k h z t e st t o n e s a m p le d a t 6 4 k h z. t h e pl ot sho w s t h e c h ar ac te r i st ic sh a p e d noi s e f l o o r o f a sig m a- de lt a co n v er t e r , w h ich is in i t ia l l y f l a t in t h e b a n d o f in t e r e st b u t t h e n r i s e s wi t h in cre a sin g f r e q uen c y . i f a s u i t ab le dig i t a l f i l t er is a p plie d t o t h is sp e c t r um, t h e n o is e f l o o r ca n b e e l im in a t e d i n t h e hig h er f r e q uen c ies. this sig n a l ca n t h en b e us ed in ds p algo r i thm s o r can be f u r t her p r o c es s e d in a d e ci ma ti o n alg o ri th m t o r e d u ce th e e f f e cti v e sa m p le ra t e . f i gur e 26 sh o w s th e r e s u l t in g sp ec tr um f o l l o w ing th e f i l t er in g a nd decima t i o n o f th e sp ec tr um o f f i gur e 25 f r o m 64 kh z t o an 8 k h z r a te. the ad73322 l als o f e a t ur es dir e c t s a m p l i n g a t th e lo w e r ra t e of 8 khz. thi s is a c hie v e d b y t h e us e o f ex tende d de cim a t i o n r e g i st ers wi t h i n t h e de cim a t o r blo c k, w h ich a l lo ws fo r t h e in cr e a s e d w o rd g r o w t h ass o c i a t e d wi t h t h e hig h er ef fe c t i v e o v e r sa m p lin g ra ti o . f i gur e 27 deta ils th e s p ectr um o f a 1 kh z te st tone c o n v e r te d a t an 8 k h z r a te. the de v i ce fe a t ur es a n o n -chi p , mas t er clo c k divider cir c ui t t h a t al lo ws t h e s a m p le ra t e t o be r e d u ce d be c a us e t h e s a m p lin g ra te of t h e s i g m a - d e lt a c o n v e r te r i s prop or t i on a l to t h e output of t h e mclk divi der (w h o s e def a u l t st a t e is divi de- b y - o n e). t h e d e ci m a t o r s f r eq u e n c y r e s p o n se (s in c 3 ) gi v e s so m e pa s s - b a nd a t te n u a t ion (u p to f s / 2 ) w h i c h c o n t i n u e s t o r o l l of f a b ov e t h e n y q u ist f r e q uen c y . i f i t is r e q u ir e d t o im ple m e n t a dig i t a l f i lte r to c r e a te a sh ar p e r c u tof f ch ar a c te r i st i c , i t ma y b e pr u d e n t t o us e a n ini t ial s a m p le ra te o f g r ea t e r than twic e the n y q u is t r a te i n orde r to a v oi d a l i a s i ng du e to t h e s m o o t h rol l - o f f of t h e sin c3 f i l t er r e s p o n s e . 00691-025 frequency (hz) 1 0 4 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 db 0 ?4 0 ?2 0 ?6 0 ?8 0 ?100 ?120 ?140 f i g u re 25. fft (a d c 64 k h z s a mp li ng ) 00691-026 frequency (hz) 4000 0 500 1000 1500 2000 2500 3000 3500 db 0 ?2 0 ?4 0 ?6 0 ?8 0 ?100 ?120 f i g u re 26. fft (a d c 8 k h z f ilt ered an d d e ci m a ted f r o m 64 k h z) 00691-027 frequency (hz) 4000 0 500 1000 1500 2000 2500 3000 3500 db 0 50 100 150 f i gure 27. fft (ad c 8 kh z d i rec t s a m p ling)
ad73322l rev. a | page 30 of 48 i n t h e cas e o f v o ice-b a nd p r o c essin g w h er e 4 kh z r e p r es e n ts t h e n y q u is t f r eq uenc y , if th e sig n al to be m e as ur e d w e r e ext e r n al l y ba nd-l i mi t e d , t h en a n 8 kh z s a m p lin g r a t e w o u l d s u f f i ce . h o w e ver , if t h e b a ndwi d t h m u st b e l i m i te d wi t h a dig i t a l f i l t er , th en i t ma y be m o r e a p p r o p r i a t e t o us e a n ini t ial s a m p lin g ra te o f 16 kh z and to p r o c ess t h is s a m p le st r e am wi t h a f i l t er i n g an d de cim a t i ng a l gor i t h m t o achi e v e a 4 k h z b a n d - l imi t e d s i g n a l a t a n 8 kh z ra t e . f i gur e 19 details th e ini t ial 16 kh z s a m p led t o ne . 00691-028 frequency (hz) 8000 0 1000 2000 3000 4000 5000 6000 7000 db 0 ?40 ?20 ?60 ?80 ?100 ?120 ?140 f i g u re 28. fft (a d c 16 k h z d i r e c t s a mpl i ng ) f i gur e 29 sh o w s th e s p ectr um o f th e f i n a l 8 kh z sa m p led fi l t e r e d t o n e . 00691-029 frequency (hz) 4000 2500 3000 3500 0 500 1000 1500 2000 db 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 f i g u re 29. fft (a d c 8 k h z f ilt ered an d d e ci m a ted f r o m 16 k h z) enc o der g r oup del a y w h en p r og ra mm e d f o r hig h s a m p lin g r a t e s, t h e ad73322l o f f e rs a v e r y lo w le ve l o f g r o u p dela y , which is g i v e n b y group d e l a y ( d e c i m a t or ) = or d e r (( m ? 1)/2) t de c w h er e: or d e r i s t h e ord e r of t h e d e c i m a tor ( = 3 ) m is t h e decima tio n fac t o r (= 32 @ 64 kh z, = 6 4 @ 32 kh z, = 128 @ 16 kh z , = 256 @ 8 kh z) t de c is t h e decima tio n s a m p le in t e r v al (= 1/2.0 48e6 bas e d o n d m clk = 16.384 mh z) c o n s ider a s e cond exa m ple: gr oup d e l a y (decima t o r @ 64 kh z) = 3 (32 ? 1)/2 (1/2.048e6) = 22.7 s i f f i na l f i l t er in g is im ple m e n t e d in t h e ds p , t h e f i na l f i l t er s g r o u p del a y m u st b e t a k e n i n to acco un t w h e n c a lc u l a t in g ov e r a l l g r o u p d e l a y . dec o der s e c t ion the de co der s e c t io n u p d a tes (s a m ples) a t t h e s a m e r a te as t h e en co der s e c t io n . this ra te is p r og ra mma b l e as 6 4 khz, 32 k h z, 16 kh z, o r 8 kh z (f r o m a 16.384 mh z m c l k ). the deco der s e c t io n r e p r es e n ts a re v e rs e o f t h e p r o c e s s t h a t was des c r i b e d i n t h e enco der s e c t io n. i n t h e cas e o f t h e de co der s e c t io n, s i g n a l s a r e a p plie d i n t h e fo r m o f s a m p les a t a n ini t i a l lo w ra t e . this s a m p le r a te is t h e n i n cr e a s e d to t h e f i na l dig i t a l sig m a- d e l t a m o d u la t o r ra te o f d m clk/8 b y in t e r p o l a t in g n e w sam p les b e tw e e n t h e o r i g ina l s a m p les. t h e in t e r p ola t in g f i l t er a l s o has t h e ac t i o n o f c a n c e l i n g im a g es d u e t o t h e in t e r p ola t ion p r o c ess usin g sp e c t r a l n u l l s t h a t exist a t in teger m u l t i p les o f t h e i n i t i a l s a m p ling ra t e . f i gur e 30 sh o w s t h e sp e c tral r e s p o n s e o f t h e de co der s e c t io n s a m p lin g a t 64 khz. a g a i n, i t s sig m a- delt a m o d u l a t o r s h a p es t h e n o i s e s o i t is r e d u ce d in t h e v o ic e b a ndwi d t h dcC 4 khz. f o r im p r o v e d vo ice - b a nd s n r , t h e us er ca n im p l em en t a n i n i t i a l a n ti- i m a gin g f i l t e r , p r eced ed b y 8 kh z t o 64 khz i n t e r p ola t ion, i n t h e ds p . 00691-030 frequency (hz) 1 0 4 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 db 0 ?20 ?10 ?40 ?30 ?60 ?50 ?80 ?70 ?90 ?100 f i g u re 30. fft (da c 64 k h z s a mp li ng )
ad73322l rev. a | page 31 of 48 b e ca us e t h e ad73322l ca n be op era t e d a t 8 kh z (s ee f i gur e 31) o r 16 kh z s a m p lin g ra t e s, which mak e i t p a r t ic u l a r l y s u i t e d f o r vo ice-b a nd p r o c essing, t h e us e r m u st u n derst a nd t h e ac t i on o f t h e in t e r p ola t o r s sin c3 r e s p on s e . a s was t h e cas e w i t h t h e en co der s e c t io n , if t h e o u t p u t si g n a l s f r e q uen c y r e sp o n s e is n o t b o u n de d b y t h e n y q u ist f r e q ue n c y , i t ma y b e ne cess a r y to p e r f o r m s o m e i n i t ia l dig i t a l f i l t er in g t o e l im ina t e sig n a l e n erg y a b o v e n y q u i s t to en sur e t h a t i t i s n o t ima g e d a t t h e in t e ger m u l t i p les o f t h e s a m p ling f r e q uen c y . i f t h e us er ch o o s e s t o by p a s s t h e i n t e r p o l at o r , p e r h ap s t o r e d u c e g r o u p d e l a y , i m a g e s o f t h e o r ig in a l s i g n a l a r e ge n e ra t e d a t i n t e ger in t e r v a l s o f t h e s a m p ling f r eq uen c y . i n this cas e th es e ima g es m u s t be r e m o v e d b y ext e rn al a n alog f i l t eri n g. 00691-031 frequency (hz) 4000 0 500 1000 1500 2000 2500 3000 3500 db 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 f i g u re 31. fft (da c 8 k h z s a mpl i ng ) f i gur e 32 sh o w s th e o u t p u t sp ec tr um o f a 1 kh z t o n e g e n e r a t e d a t a n 8 kh z s a m p lin g ra te wi t h t h e in t e r p ola t o r b y p a s s e d . 00691-032 frequency (hz) 1 0 4 3.5 0 0.5 1.0 1.5 2.0 2.5 3.0 db 0 ?10 ?30 ?20 ?40 ?50 ?70 ?60 ?90 ?80 ?100 f i gure 32. fft (d a c 8 kh z s a mplingi nt erpolator b y passed) on- c hip fil t ering the p r ima r y f u n c t i on o f t h e sys t em f i l t er in g s sin c -c ub e d (sin c3) r e sp o n s e is t o e l i m in a t e a l ia s e s o r ima g es o f t h e a d cs or d a c s re s a mp l i ng , re s p e c t i v e ly . b o t h mo d u l a tor s are s a m p l e d a t a n o minal ra te o f d m clk/8 (whic h is 2.048 mh z f o r a d m clk o f 16.384 mh z), and t h e sim p le , ext e r n al r c a n t i al ias f i l t er is s u f f i cien t t o p r o v i d e t h e r e q u ir e d st o p -b a nd r e je c t ion a b o v e t h e n y q u is t f r e q uen c y fo r t h is s a m p le ra te . i n t h e cas e o f t h e ad c s e c t ion, t h e de cima t i n g f i l t er is r e q u i r e d t o b o t h d e c r ea se sa m p l e ra t e a n d in c r ease sa m p l e r e so l u ti o n . t h e p r o c es s o f c h a n g i n g s a m p l e ra te (r es a m p l in g) l e ads t o al ias e s of t h e o r ig ina l s a m p le d wa v e fo r m a p p e a r in g a t i n teger m u l t i p les of t h e ne w s a m p le ra t e . th e s e al ias e s w o u l d g e t ma p p e d in t o t h e r e q u ir e d sig n a l p a ss b a nd wi t h ou t t h e a p pl ic a t ion o f s o me f u r t h e r a n t i al ias f i l t er in g. i n the ad73322l, t h e sin c -c ubed r e s p o n se o f t h e d e ci ma ti n g f i l t er cr ea t e s s p ectral n u ll s a t in t e g e r mu l t i p l e s o f t h e n e w s a mp l e r a t e . t h e s e nu l l s c o i n c i d e w i t h t h e a l ia s e s o f t h e o r i g ina l w a v e fo r m , w h ich w e r e cr e a t e d b y t h e do wn -s a m pl in g p r o c ess, t h er efo r e r e d u cin g o r e l im in a t in g t h e a l i a s i n g du e t o s a m p l e r a t e r e du c t i o n . i n th e d a c s e cti o n , i n c r e a s i n g th e s a m p l i n g r a t e b y in t e r p ol a t ion cr e a t e s ima g es o f t h e o r ig ina l wa vefo r m a t in t e r v a l s o f t h e o r ig ina l s a m p l i n g f r e q uen c y . t h es e im a g es ma y be s u f f i ci en tl y r e ject e d b y e x t e rn al ci r c ui tr y b u t th e si n c - c ube d f i l t er in t h e in t e r p ola t o r a g a i n n u l l s t h e o u t p u t sp e c t r um a t in teger in t e r v a l s o f t h e o r ig in a l s a m p ling ra t e , w h ich co r r es p o n d s wi t h t h e ima g es d u e t o t h e i n t e r p ol a t io n p r o c e s s. the s p e c tral r e sp o n s e o f a sin c -c u b e d f i l t er sho w s the c h a r ac- t e r i s t ic n u l l s a t in t e g e r in ter v als o f th e s a m p ling f r e q uen c y . i t s p a ss-b an d ch a r ac t e r i st ic (u p t o n y q u ist f r e q ue n c y ) fe a t ur es a r o l l -o f f t h a t co n t in ues u p t o t h e s a m p ling f r e q uen c y , w h er e t h e f i rst n u l l o c c u rs . i n man y a p plic a t io n s t h is smo o t h r e sp o n s e do es n o t g i v e s u f f i cien t a t t e n u a t io n o f f r e q uen c i e s o u tside t h e b a nd o f in t e r e s t ; t h er efo r e , i t ma y b e n e ces s a r y to im ple m en t a f i na l f i l t er in t h e ds p to e q ua l i ze t h e p a ss-b and r o l l -o f f a n d p r o v id e a sha r p e r t r a n si t i o n b a nd an d g r e a ter sto p -b and a tte n u a t i o n. dec o der g r oup del a y the i n ter p ol a t or r o l l -o f f is main ly d u e to its si n c -c ub e d f u n c t i on cha r ac t e r i st ic, w h ich h a s a n i n her e n t g r o u p de l a y g i v e n b y th e e q u a ti o n gr oup d e l a y ( i nte r p o la t o r ) = or d e r ( l ? 1)/2) t int w h er e: or d e r i s t h e i n te r p o l a t or ord e r ( = 3 ) . l is t h e in t e r p ol a t io n f a c t o r (= 32 @ 64 kh z, = 6 4 @ 32 kh z, = 128 @ 16 kh z, = 256 @ 8 kh z). t int is th e in t e r p ola t ion s a m p le in t e r v al (= 1/2. 048e6). c o n s ider a s e cond exa m ple: gr oup d e l a y (i n t er po l a to r @ 64 kh z) = 3 (32 ? 1)/2 (1/2.048e6) = 22.7 s the a n a l o g s e c t io n has a g r o u p dela y o f a p p r o x i m a t ely 25 s.
ad73322l rev. a | page 32 of 48 design consi d era t ions the ad73322 l f e a t ur es both dif f er en tial in p u ts a nd o u t p u t s on e a ch ch a n nel to pro v i d e opt i m a l p e r f or m a nc e an d avoi d co mm on- m o d e n o is e. i t is als o p o s s i b le t o in t e r f ace ei t h er in p u ts o r o u t p uts in s i n g le -e n d e d m o d e . this s e c t io n d e t a i l s t h e ch o i ce o f i n p u t a nd o u tp u t co nf igur a t io n s and a l s o g i ves s o m e t i ps t o w a r d s suc c essf u l co nf igura t io n o f t h e a n a l og in t e r f ac e secti o n s . continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/ ? 15db pga 0/38db pga gain 1 refout refcap reference v ref 00691- 033 0.047 f 0.047 f 100 ? 100 ? 0.1 f anti-alias filter f i gure 33. a n alog i n put (dc- c o upled) anal og input s ther e a r e s e veral dif f er en t w a y s in w h ich t h e analog in p u t (en c o d er) s e c t ion o f the ad733 22l ca n be in t e r f aced t o ext e r n al cir c ui tr y . i t p r o v ides o p tio n al in p u t am p l if iers which al lo w s o ur ces w i t h hig h s o ur ce im p e dan c e t o dr i v e t h e ad c s e c t io n co r r e c t l y . w h e n t h e i n pu t a m plif iers a r e ena b le d , t h e in p u t cha n ne l is co nf igur e d as a dif f er en t i a l p a ir o f in v e r t in g am p l i f i e r s re f e re nc e d to t h e i n t e r n a l re f e re nc e ( r e f c a p ) l e ve l . the i n v e r t in g t e r m ina l s o f t h e i n p u t am plif ier p a ir a r e desig n a t e d as pi n s vinp1 and vin n 1 fo r c h a nnel 1 (vi n p2 a nd vi nn2 fo r c h a nnel 2). t h e a m plif ier fe e d b a ck co n n e c t i o n s a r e a v a i la b l e o n pin s vf bp1 and vf bn1 fo r c h a nnel 1 (vf b p 2 a nd vf bn2 fo r c h a nnel 2). f o r a p plica t ion s w h er e ext e r n a l sig n a l b u f f er in g is r e q u ir e d , t h e in p u t am plif iers ca n b e b y p a ss e d and t h e a d c dr i v e n dir e c t l y . w h e n t h e in pu t am plif i e rs a r e dis a b l e d , t h e s i g m a- de l t a m o d u l a t o r s in p u t s e c t io n (sc pga) is acc e ss e d dir e c t ly thr o ug h t h e vfb p 1 an d vf b n 1 p i n s f o r cha nne l 1 (vfb p2 a nd vf bn2 fo r c h a nnel 2). i t is als o p o s s i b l e t o dr i v e t h e a d cs i n ei t h er di f f er en t i al o r sin g le-e nde d mo des. i f t h e s i n g le-e n d e d m o d e is ch o s e n , i t is p o s s i b le using s o f t wa r e co n t r o l t o m u l t i p lex be tw e e n tw o sin g l e - ende d in pu ts conn e c te d to t h e p o si t i ve and n e ga t i ve i n p u t p i ns. the p r ima r y co n c er n s in in t e r f acin g t o t h e ad c a r e , f i rst, t o p r o v ide ade q u a te a n t i al ias f i l t er i n g a nd t o ens u re t h a t t h e sig n al s o ur ce dr i v es t h e sw i t ch e d -c a p aci t o r in p u t o f t h e ad c co r r e c tl y . the sig m a-de l t a desig n o f the ad c and i t s o v er - s a m p ling c h a r ac t e r i s t ics sim p lif y th e a n t i alias r e q u ir e m en ts, b u t t h e s i n g le -p ole rc f i l t er is p r ima r i l y in t e nde d t o e l im in a t e a l ias i n g o f f r e q uen c ies a b o v e t h e n y q u ist f r e q u e n c y o f t h e sig m a-de l t a m o d u l a t o r s s a m p lin g ra t e ( t yp ical ly 2.048 mh z). i t ma y st i l l r e q u ire a m o r e sp e c if ic dig i t a l f i l t er i m ple m en t a t i on in t h e ds p t o p r o v ide t h e f i nal sig n al-f r e q u en c y r e s p o n s e char ac ter i st ic s . f o r opt i m u m p e r f or m a nc e, t h e c a p a c i tor s u s e d f o r t h e a n t i al iasin g f i l t er m u s t b e o f hig h q u ali t y die l ec t r ic (npo). a s e co nd con c er n is in t e r f ac in g t h e sig n a l s o ur ce t o t h e ad c s s w itc h e d c a p a c i tor i n pu t l o a d . t h e s c i n pu t pre s e n t s a c o m p l e x d y na mic lo ad t o a sig n al s o ur ce, t h er efo r e , n o t e t h a t t h e s l e w ra t e cha r ac t e r i st ic is a n i m p o r t an t co n s i d era t ion w h e n ch o o sing ext e r n al b u f f ers f o r us e wi th the ad73322l. the in t e r n al in ver t in g o p a m ps o n the ad73 322l a r e s p ecif ical l y desig n ed to i n t e r f a c e to t h e a d c s s c i n put st age. the ad73322l s o n -c hi p 38 db p r ea m p lif i er can b e ena b le d w h en t h er e is no t en o u g h ga i n in t h e in p u t cir c ui t; t h e p r e - a m plif ier is co n f igur e d b y b i ts igs0-2 o f crd . the t o t a l ga in m u st b e c o nf ig u r e d to e n su re t h a t a f u l l -s c a l e in p u t s i g n a l p r o d uces a sig n al le v e l a t t h e i n p u t t o t h e sig m a-del t a m o d u la t o r o f th e a d c tha t d o es n o t e x cee d t h e m a xi m u m in p u t ra n g e . the dc b i as in g o f t h e a n a l og in p u t sig n a l is ac c o m p lish e d w i t h a n o n -chi p v o l t a g e r e f e r e n c e . i f th e in p u t sig n a l is n o t b i as e d a t t h e i n t e r n a l re f e re nc e l e v e l ( v i a r e f o u t ) , t h e n it m u st b e a c - c oupl e d w i t h e x te r n a l c o upl i ng c a p a c i tors . c i n s h ou l d b e 0.1 f o r la rg er . the dc b i as in g o f th e in p u t can th en be acco m p lish e d usin g r e sis t o r s t o refo ut , as f i g u r e 36 a nd f i gur e 37 sh o w . continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/ ?15db pga 0/38db pga gain 1 refout refcap reference v ref 0.047 f 0.047 f 100 ? 100 ? 0.1 f 00691- 034 optional buffer anti-alias filter f i gure 34. a n alog i n put (dc- c o upled) using ex t e rnal a m plifiers
ad73322l rev. a | page 33 of 48 the ad73322l s ad c in p u ts a r e b i as e d abo u t t h e in t e r n al r e f e r e n c e le ve l (refcap le ve l); th er ef o r e , i t ma y be n e ces s a r y t o b i as ext e rn al si gn als t o th i s le v e l usi n g t h e b u f f er ed refo ut le v e l as t h e r e fer e n c e . this is a pplica b le in e i t h e r dc-co u ple d o r ac-co u ple d co nf igura t io n s . i n t h e cas e o f dc couplin g , t h e sig n a l (b ia s e d to ref o ut) m a y b e a p plie d dir e c t ly to t h e i n p u ts (usin g a m p l if ier b y p a s s ), as sh o w n in f i gur e 33 , o r i t ma y be co ndi tion e d in a n ext e r n al o p am p w h er e i t can als o be b i as ed to t h e re f e re nc e l e vel u s i n g t h e bu f f e r e d r e f o u t s i g n a l , a s s h o w n in f i gur e 34, o r i t is p o s s ib le t o co nn ec t in p u ts dir e c t l y to th e ad73322l s in p u t o p a m ps as s h o w n in f i gu r e 35. continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/?15db pga 0/38db pga gain 1 refout refcap reference v ref 50k ? 50k ? 50k ? 50k ? 0.1 f 00691-035 100pf 100pf f i g u re 35. a n a l og i n put ( d c coup led) u s ing inte rna l a m plif i e rs i n t h e cas e o f ac co u p lin g , a c a p a ci t o r is us ed t o co u p le the sig n al t o t h e i n pu t o f t h e ad c. the ad c i n p u t m u s t b e b i as e d t o t h e in t e r n a l refer e n c e (refc a p) le v e l w h ich is do n e b y co n n ect i n g th e in p u t t o th e r e fo u t p i n t h r o ugh a 10 k ? re s i stor , as show n i n f i g u re 3 6 . continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/?15db pga 0/38db pga gain 1 refout refcap reference v ref 100 ? 100 ? 0.1 f 0.1 f 0.1 f 00691-036 0.047 f 0.047 f 10k ? 10k ? f i g u re 36. a n a l og i n put (a c- coupled) d i f f e r e nt ia l i f t h e ad c is b e in g co n n e c te d in si n g le-e nde d m o de, t h e ad73322l sh ou ld be p r og ra mm e d f o r sin g le-ended m o de usin g t h e s een a nd in v b i ts o f crf a nd t h e in p u ts co n n e c te d a s sh ow n i n fi g u re 3 7 . whe n o p e r a t e d i n s i ng l e - e nd e d i n put m o de , t h e ad7 3322l ca n m u l t i p lex o n e o f the tw o in p u ts t o t h e ad c i n p u t. continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/?15db pga 0/38db pga gain 1 refout refcap reference v ref 100 ? 0.1 f 0.1 f 0.047 f 10k ? 00691-037 f i gure 37. a n alog i n put ( a c- c o upled) single-ended i f b e st p e r f o r ma n c e is r e q u ir e d f r o m a sin g l e -e nde d s o ur c e , i t is p o s s i b le t o co nf igur e the ad73 322l s in p u t a m p l if iers as a sin g le-e nde d-t o -dif fer e n t ia l con v er t e r , as sh o w n in f i gur e 38. continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/? 15db pga 0/38db pga gain 1 refout refcap reference v ref 50k ? 50k ? 50k ? 50k ? 0.1 f 100pf 100pf 00691-038 f i g u re 38. sing l e -e nded-to - d i f f e rent i a l conve r s i on on a n al og input
ad73322l rev. a | page 34 of 48 interf a c i n g t o an ele c tre t microph o ne f i gur e 39 d e t a ils a n in t e rfa c e f o r a n e l ectr e t m i cr o p h o n e whi c h ma y b e us e d in s o me v o ice a p pl ica t io n s . e l e c t r e t micr o p h o n e s ty p i c a l l y fe a t ur e a fet am plif ie r w h os e ou t p u t is access e d o n t h e s a m e le ad w h ich s u p p lies p o w e r t o t h e micro p h o n e ; th e r e f o r e , th i s o u t p u t si gn al m u s t b e ca pa ci ti v e ly co u p led t o r e m o v e the p o wer s u p p l y (dc) co m p on en t. i n t h is cir c ui t, t h e ad73322l in p u t c h a n n e l is bein g us ed in sing l e -en d e d m o de w h er e t h e i n t e r n a l i n v e r t in g am plif ier p r o v id es sui t ab le ga i n t o s c ale t h e i n p u t s i g n al r e la t i v e t o t h e ad c s f u l l -s cale i n p u t ra n g e . th e b u f f er e d in t e r n al r e fer e n c e l e v e l a t r e fo u t is us e d v i a an ext e r n al b u f f er t o p r o v ide p o w e r t o t h e ele c t r et micr o p h o n e . t h is p r o v i d es a quiet, st a b le su p p ly fo r t h e micr o p h o n e . i f t h is is n o t a concer n, t h en t h e micr o p h o n e can b e p o we re d f r om t h e s y ste m p o we r su p p ly . continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/ ?15db pga 0/38db pga gain 1 refout refcap reference v ref r1 r b r a 50k ? c refcap 100pf c2 electricity probe 10 f 5v 00691- 039 f i gure 39. e l ec t r et m i croph o ne inte r f ac e c i r c u i t anal og ou tput the ad73322l s dif f er en tial a n alog o u t p u t ( v o u t) is p r o d uc ed b y a n on-chi p dif f er en t i al am pli f ier . th e dif f er en t i al o u t p u t can b e ac -co u ple d or dc-co u ple d dire c t ly t o a lo ad w h ich c a n b e a h e ad s e t o r t h e i n p u t o f an ext e r n a l a m plif ier (t h e sp e c if ie d minim u m r e sis t i v e lo ad o n t h e o u t p u t s e c t ion is 150 ?.) i t is p o s s i b le t o co nn e c t t h e o u t p u t s in e i t h er a dif f er en t i al o r a sin g le-e nde d co nf igur a t io n, b u t ple a s e n o te t h a t t h e ef fe c t i v e max i m u m o u t p u t vol t a g e s w in g (p e a k to p e a k ) is ha lve d i n t h e cas e o f sin g l e -e n d e d co nn e c t i on. f i gur e 40 sh o w s a sim p le cir c ui t p r o v i d ing a dif f er en t i al o u t p ut w i t h ac c o u p lin g . th e ca p a ci t o rs in this cir c ui t (c ou t ) a r e o p t i o n al; if us e d , t h eir v a l u e ca n be ch os en as f o l l o w s: load out r fc c = 2 1 w h er e f c = desire d c u to f f f r e q uen c y . continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/ ? 15db pga gain 1 refout refcap reference c refcap r load c out c out 00691-040 f i gure 40. e x a m pl e circuit fo r d i fferent ia l o u tput fi g u r e 4 1 s h ow s a n e x a m p l e c i r c u i t f o r pr ov i d i n g a s i n g l e - e n d e d output w i t h a c c o upl i ng . t h e c a p a c i tor of t h i s c i rc u i t ( c ou t ) is not opt i on a l i f d c c u r r e n t d r ai n i s to b e a v oi d e d. 00691-041 continuous time low-pass filter v ref vfbn1 vinn1 vinp1 vfbp1 voutp1 voutn1 ad73322l +6/ ? 15db pga gain 1 refout refcap reference 0.1 f r load c out f i gure 41. e x a m pl e circuit fo r s i ngl e -e nded o u tput
ad73322l rev. a | page 35 of 48 differential - t o - single-ended output i n s o me a p pli c a t io n s i t ma y b e desira b l e t o con v er t t h e f u l l dif f er en t i a l o u t p u t o f t h e de co de r cha nnel to a si n g le-e nde d s i g n a l . t h e c i rc u i t of f i g u re 4 2 sh o w s a s c he me f o r d o i n g t h i s . continuous time low-pass filter v ref vinp1 vfbp1 voutp1 voutn1 ad73322l +6/?15db pga 0/38db pga gain 1 refout refcap reference v ref 0.1 f 00691- 042 r f r1 r1 r f r load f i gure 42. e x a m pl e circuit fo r d i fferent ia l to s i ngl e -e nded ou t p u t c o n v e r si o n digit a l interf a c ing the ad73322 l is desig n ed t o in t e r f ac e easil y to m o s t co mm on d s p s . t h e s c l k , sd o , sd o f s , sdi , an d sdi f s m u s t b e c o n - n e c t e d t o t h e d s p s s e r i al clo c k, r e cei v e da t a , r e cei v e da t a f r a m e sy n c , tran smi t da t a , an d tra n smi t da ta f r a m e sy n c p i n s , re sp e c t i v e ly . t h e s e p i n m a y b e c o n t rol l e d f r o m a p a r a l l el output pi n or f l ag pi n su c h a s f l 0 - 2 on t h e a d sp - 2 1 x x ( o r x f o n t h e t m s320 c5x) o r , w h er e s p o r t p o w e r - do wn is n o t r e q u ir e d , i t can b e p e r m an en t l y st ra p p e d hi g h usin g a su i t a b l e pu l l - u p re s i s t or . t h e res e t p i n ma y b e co nne c t e d to t h e s y ste m h a rd w a re re s e t st r u c t u r e or it m a y a l s o b e c o n t ro l l e d usin g a de dic a te d co n t r o l li n e . i n t h e e v en t o f ty in g i t to t h e g l ob al sys t em r e s e t, i t is ad vis a b l e t o o p era t e t h e de vice in mixe d m o de , w h ich al l o ws a s o f t wa r e res e t, o t h e r w is e t h er e is n o co n v enien t wa y o f r e s e t t in g t h e de vic e . f i gur e 4 3 a nd f i gur e 44 s h o w typ i ca l co nn ec t i o n s t o an ads p -218x a n d t m s320c5x, re sp e c t i v e ly . tfs dt sclk dr rfs adsp-218x dsp ad73322l codec sdifs sdi sclk sdo sdofs fl0 fl1 reset se 00691- 043 f i g u re 43. a d 7 3 3 2 2 l co nnec t ed t o a d sp - 2 18x fsx dt clkx dr fsr tms320c5x dsp ad73322l codec sdifs sdi sclk sdo sdofs xf reset se clkr 00691- 044 f i gur e 4 4 . ad73 322 l c o nne c t e d to tms3 20 c5 x c a sc ade oper a t ion w h er e i t is r e q u ir e d t o co nf igure a ca s c a d e o f up t o eig h t co de c s (f o u r ad73322l d u al co dec s ), en s u r e tha t t h e t i min g o f the s e a nd res e t sig n als is syn c hr o n ize d a t e a c h de vice in t h e cas c a d e . a si m p le d- typ e f l i p -f lo p is suf f i cien t to syn c e a ch sig n al t o t h e mas t er clo c k mcl k , as i n f i gur e 45. 1/2 74hc74 clk dq dsp control to se mclk se signal synchronized to mclk 1/2 74hc74 clk dq dsp control to reset mclk reset signal synchronized to mclk 00691- 045 f i g u re 45. se and reset s y nc cir c u i t or casc aded o p er ation c o n n e c t i o n of a c a s c a d e of d e v i c e s to a d s p , a s sh ow n i n f i gur e 46, is n o m o r e co m p l i c a ted than co nn ec t i n g a sin g le de vic e . i n ste a d o f co nn e c t i n g t h e sd o an d sd of s to t h e d s p s rx p o r t , t h e s e ar e n o w da isy - ch a i ne d to t h e s d i a nd s d if s o f t h e n e xt de vi ce in t h e cas c ade . the s d o and sd o f s o f t h e f i nal de vice in t h e cas c ade a r e co nn e c t e d t o t h e ds p s rx p o r t t o co m p let e t h e ca s c ad e. s e an d res e t o n all devi ce s a r e f e d f r o m t h e s i gn a l s t h a t w e r e s y n c h r o n i z e d w i th th e m c l k u s i n g th e c i rc u i t , a s d e s c r i b e d pre v i o u sly . t h e s c l k f r om on ly one d e v i c e n e e d b e co n n e c te d to t h e ds p s sclk i n p u t(s) as a l l de vices r u n a t t h e s a me scl k f r e q uen c y a nd phas e.
ad73322l rev. a | page 36 of 48 grounding and l a y o ut digital ground analog ground 00691-047 b e ca us e t h e a n a l og in p u ts t o the ad73322l a r e dif f er en tial , mo st of t h e volt age s i n t h e an a l o g mo d u l a tor are c o m m on - m o de v o l t a g es. the exce l l e n t comm on- m o d e r e je c t io n o f t h e p a r t r e m o v e s co mm on- m o d e no is e o n t h es e i n p u ts. the a n alog a nd dig i t a l s u p p lies o f th e ad73 322l a r e indep e n d en t and s e p a ra te ly p i nne d o u t t o mini mi ze co u p li n g b e tw e e n a n a l og and d i gi tal sec t i o n s o f th e de v i ce . th e d i g i tal f i l t e r s o n t h e en co d e r s e c t io n wi l l p r o v id e r e j e c t io n o f b r o a d b and n o is e o n t h e p o w e r s u p p lies, excep t a t in teg e r m u l t i p les o f th e m o d u la t o r s a m p lin g f r e q uen c y . th e dig i t a l f i l t ers als o r e m o v e n o is e f r o m t h e a n alog in p u ts p r o v ide d t h e n o is e s o ur c e do es n o t s a t u r a t e t h e a n alog m o d u l a t o r . h o w e v e r , bec a us e t h e r e s o l u tion o f th e ad73322l s ad c is hig h , and t h e n o is e l e v e l s f r o m th e ad7 3322l a r e s o lo w , c a r e m u st b e t a k e n w i t h r e g a r d to g r o u nding a nd l a yo u t . f i g u re 47. ground p l an e lay o ut a v o i d r u nnin g dig i t a l li n e s und e r t h e de vic e b e ca us e t h e y co u p le n o is e o n t o t h e di e . th e analog g r o u n d pl a n e sh o u ld b e al lo w e d t o r u n un der the ad7 3322l t o a v o i d n o is e cou p ling. the p o wer s u p p l y lin e s t o t h e ad73322l sh o u l d us e as la rg e a t r ace as p o ssib le t o p r o v id e lo w im p e dan c e p a t h s a nd r e d u ce t h e ef fe c t s o f g l i t c h e s o n t h e p o w e r su p p l y lin e s. f a st swi t c h in g sig n als, s u c h as c l o c ks, sh o u l d b e s h ie lde d wi t h dig i tal g r o u n d to a v oi d r a d i a t i n g noi s e to ot he r s e c t i o ns of t h e b o ard. c l o c k sig n als sh o u ld ne v e r b e r u n ne ar th e a n alog in p u ts. t r aces on o p p o si t e sides o f th e bo a r d sh ou ld r u n a t r i g h t a n g l es t o e a ch o t h e r . this r e d u ces t h e ef fe c t s o f fe e d t h r o ug h on t h e b o a r d . a mi c r o s t r i p te ch ni qu e i s b y f a r t h e b e s t to u s e, but i s not a l w a y s p o s s i b le wi t h a do u b le -side d bo a r d . i n this t e chniq u e , t h e co m p on e n t sid e o f t h e b o a r d is de di ca te d to g r o u nd plan es, w h i l e sig n als a r e place d o n t h e o t h e r side . tfs dt dr rfs ad73322l codec sdifs sdi sclk sdo sdofs sclk device 1 mclk se reset ad73322l codec sdifs sdi sclk sdo sdofs device 2 mclk se 74hc74 q1 q2 d1 d2 fl0 fl1 adsp-218x dsp 00691-046 reset g o o d de co u p l i n g is im p o r t a n t w h en usin g hig h sp e e d d e vices. on t h e ad7332 2l, bo t h t h e r e f e r e n c e (refcap) a n d s u p p lies n e e d to b e de cou p le d . i t is r e co mmende d t h a t t h e de co u p li n g ca p a ci t o rs us ed o n bo t h refcap a nd t h e su p p lies be p l aced as cl o s e as p o ss ibl e to t h e i r re sp e c t i ve p i ns to e n su re hig h p e r f o r ma n c e f r o m t h e de vice . al l a n alog an d dig i tal s u p p lies sh o u l d b e de cou p le d to a g n d a nd d g nd r e sp e c t i vely , wi t h 0.1 f cera mic ca p a ci t o rs in p a ral l e l wi t h 10 f ta n t al u m ca p a ci t o rs. i n sys t em s w h er e a c o mm on-su p pl y v o l t a g e is us e d t o dr i v e bo t h t h e a v d d an d d v d d o f the ad73322l, i t is re c o mme nde d t h a t t h e s y ste m s a v dd su p p ly b e u s e d . t h is su p p ly shou l d h a ve t h e re c o m m e nde d an a l o g sup p ly de c o u p l i ng betw een t h e a v d d p i n s o f t h e ad73322l and a g nd and t h e r e co mm e nde d dig i t a l sup p ly d e co u p lin g ca p a c i to rs b e t w e e n t h e d v dd pin and d g nd . f i g u re 46. con n ec t i on of t w o a d 7 3 3 2 2 ls cas c aded to a d sp - 2 18x the p r in t e d c i r c ui t bo a r d tha t ho us es th e ad73 322l s h o u l d be desig n e d s o t h e a n a l o g a nd d i g i t a l s e c t io n s a r e s e p a r a te d and co nf in e d t o cer t a i n s e c t io n s o f t h e bo a r d . the ad73322l p i n co nf igur a t io n of fers a ma j o r ad va n t a g e i n t h a t i t s a n a l o g a nd dig i t a l i n ter f ace s a r e co nn e c te d o n o p p o si te sid e s o f t h e pa c k a g e . t h i s f a c i l i ta t e s th e u s e o f gr o u n d p l a n e s t h a t c a n b e easil y s e p a ra t e d, as s h o w n in f i gur e 47. a minim u m et ch te chni q u e is ge ner a l l y b e st fo r g r o u n d plan es b e ca us e i t g i ves t h e b e st sh iel d i n g . d i g i t a l and ana l o g g r ou nd pl ane s s h ou l d b e j o i n e d in o n ly on e place . i f t h is co nn e c t i o n is cl os e t o t h e de vic e , i t is r e commende d a fer r i te b e a d i n d u c t or b e us e d , as sh ow n i n fi g u re 4 7 .
ad73322l rev. a | page 37 of 48 dsp programming considerations this section discusses how the serial port of the dsp should be configured and the implications of whether rx and tx interrupts should be enabled. dsp sport configuration following are the key settings of the dsp sport required for the successful operation with the ad73322l: ? configure for external sclk ? serial word length = 16 bits ? transmit and receive frame syncs required with every word ? receive frame sync is an input to the dsp ? transmit frame sync is an: inputin frame sync loop-back mode outputin nonframe sync loop-back mode ? frame syncs occur one sclk cycle before the msb of the serial word ? frame syncs are active high dsp sport interrupts if sport interrupts are enabled, it is important to note that the active signals on the frame sync pins do not necessarily correspond in real time to when sport interrupts are generated. on adsp-21xx processors, it is necessary to enable sport interrupts and use interrupt service routines (isrs) to handle tx/rx activity, while on the tms320csx processors, it is possible to poll the status of the rx and tx registers. this means that rx/tx activity can be monitored using a single isr that would ideally be the tx isr because the tx interrupt typically occurs before the rx isr. dsp software considerations when interfacing to the ad73322l when choosing the operating mode and hardware config- uration of the ad73322l, be aware of their implications for dsp software operation. the user has the flexibility of choosing from either fslb or nonfslb when deciding on dsp-to-afe connectivity. there is also a choice to be made between using autobuffering of input and output samples, or simply choosing to accept them as individual interrupts. because most modern dsp engines support these modes, this section discusses these topics in a generic dsp sense. operating mode the ad73322l supports two basic operating modes: frame sync loop back (fslb) and nonfslb (see the interfacing section). as described previously, fslb has some limitations when used in mixed mode but is very suitable for use with the autobuffering feature that is offered on many modern dsps. autobuffering allows the user to specify the number of input or output words (samples) that are transferred before a specific tx or rx sport interrupt is generated. given that the ad73322l outputs two sample words per sample period, it is possible, using auto-buffering, to have the dsps sport generate a single interrupt on receipt of the second of the two sample words. additionally, both samples could be stored in a data buffer within the data memory store. this technique has the advantage of reducing the number of both tx and rx sport interrupts to a single one at each sample interval. the user also knows where each sample is stored. the alternative is to handle a larger number of sport interrupts (twice as many in the case of a single ad73322l) while also having some status flags to indicate the origin and destination of each new sample. mixed-mode operation to take full advantage of mixed-mode operation, configure the dsp/codec interface in nonfslb and disable autobuffering. this allows a variable number of words to be sent to the ad73322l in each sample periodthe extra words being control words that are typically used to update gain settings in adaptive control applications. the recommended sequence for updating control registers in mixed mode is to send the control word(s) first before the dac update word. it is possible to use mixed-mode operation when configured in fslb, but it is necessary to replace the dac update with a control word write in each sample period. this may cause some discontinuity in the output signal due to a sample point being missed and the previous sample being repeated. however, this may be acceptable in some cases as the effect may be masked by gain changes, etc. interrupts the ad73322l transfers and receives information over the serial connection from the dsps sport. this occurs following resetduring the initialization phaseand in both data mode and mixed mode. each transfer of data to or from the dsp can cause a sport interrupt to occur. however even in fslb configuration where serial transfers in and out of the dsp are synchronous, tx and rx interrupts do not occur at the same time due to the way that tx and rx interrupts are generated internally within the dsps sport. this is especially important in time-critical, control loop applications where it may be necessary to use rx interrupts only, as the relative positioning of the tx interrupts relative to the rx interrupts in a single sample interval are not suitable for quick update of new dac positions.
ad73322l rev. a | page 38 of 48 initialization following reset, the ad73322l is in its default condition, which ensures that the device is in control mode and must be programmed or initialized from the dsp to start conversions. because communications between ad73322l and the dsp are interrupt driven, it is usually not practical to embed the initial- ization codes into the body of the initialization routine. it is more practical to put the sequence of initialization codes in a data (or program) memory buffer and to access this buffer with a pointer that is updated on each interrupt. if a circular buffer is used, it allows the interrupt routine to check when the circular buffer pointer has wrapped aroundat which point the initialization sequence is complete. in fslb configurations, a single control word per codec per sample period is sent to the ad73322l. in nonfslb, it is possible to initialize the device in a single sample period provided the sclk rate is programmed to a high rate. it is also possible to use autobuffering, in which case an interrupt is generated when the entire initialization sequence has been sent to the ad73322l. running the ad73322l with adcs or dacs in power-down the programmability of the ad73322l allows the user flexi- bility in choosing what sections of the ad73322l need to be powered up. this allows better matching of the power con- sumption and application requirements, because the ad73322l offers two adcs and two dacs in any combination. the ad73322l always interfaces to the dsp in a standard way, regardless of what adc or dac sections are enabled or disabled. therefore, the dsp expects to receive two adc samples per sample period and to transmit two dac samples per sample period. if a particular adc is disabled (in power- down) then its sample value is invalid. likewise, a sample sent to a dac which is disabled has no effect. there are two distinct phases of operation of the ad73322l: initialization of the device via each codec sections control registers, and operation of the converter sections of each codec. the initialization phase involves programming the control registers of the ad73322l to ensure the required operating characteristics such as sampling rate, serial clock rate, and i/o gain. there are several ways in which the dsp can be programmed to initialize the ad73322l. these range from hard-coding a sequence of dsp sport tx register writes with constants used for the initialization words, to putting the initialization sequence in a circular data buffer and using an autobuffered transmit sequence. hard-coding involves creating a sequence of writes to the dsps sport tx buffer, which are separated by loops or instructions that idle and wait for the next tx interrupt to occur, as shown in the code that follows. ax0 = b#1000100100000100; tx0 = ax0; idle; {wait for tx register to send current word} the circular buffer approach can be useful if a long initiali- zation sequence is required. the list of initialization words is put into the buffer in the required order: .var/dm/ram/circ init_cmds[16]; {codec init sequence} .var/dm/ram stat_flag; .init init_cmds: b # 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 , b # 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 , b # 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 1 , b # 1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 1 , b # 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 , b # 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 , b # 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ; the dsp program initializes pointers to the top of the buffer: i3 = ^init_cmds; 13 = %init_cmds; and puts the first entry in the dsps transmit buffer so that it is available at the first sdofs pulse: ax0 = dm(i3,m1); tx0 = ax0; the dsps transmit interrupt is enabled: imask = b#0001000000;
ad73322l rev. a | page 39 of 48 at each occurrence of an sdofs pulse, the dsps transmit buffer contents are sent to the sdi pin of the ad73322l. this also causes a subsequent dsp tx interrupt which transfers the initialization word, pointed to by the circular buffer pointer, to the tx buffer. the buffer pointer is updated to point to the next unsent initialization word. when the circular buffer pointer wraps around, which happens after the last word has been accessed, it indicates that the initialization phase is complete. this can be done manually in the dsp using a simple address check, or autobuffered mode can be used to complete the transfer automatically. txcdat: ar = dm(stat_flag); ar = pass ar; if eq rti; ena sec_reg; ax0 = dm (i3, m1); tx0 = ax0; ax0 = i3; ay0 = ^init_cmds; ar = ax0 - ay0; if gt rti; ax0 = 0x00; dm (stat_flag) = ax0; rti; in the main body of the program the code loops, waiting for the initialization sequence to be completed. check_init: ax0 = dm (stat_flag); af = pass ax0; if ne jump check_init; because the ad73322l is effectively a cascade of two codec units, it is important to observe the following restrictions in the sequence of sending initialization words to the two codecs. it is preferable to send pairs of control words for the corresponding control registers in each codec, and it is essential to send the control word for codec 2 before that for codec 1. control registers a and b contain settings, such as sampling rate, serial clock rate, etc., which critically require synchronous update in both codecs. once the device has been initialized, control register a on both codecs is written with a control word which changes the operating mode from program mode to either data mode or mixed control data mode. the device count field, which defaults to 000b, must be programmed to 001b for a single ad73322l device. in data mode or mixed mode, the main function of the device is to return adc samples from both codecs and to accept dac words for both codecs. during each sample interval, two adc samples are returned from the device, while in the same interval two dac update samples are sent to the device. to reduce the number of interrupts and to reduce complexity, autobuffering can be used to ensure that only one interrupt is generated during each sampling interval.
ad73322l rev. a | page 40 of 48 dac timing control example the ad73322l s d a c is lo ade d f r o m th e d a c r e g i s t er co n t en ts j u s t b e fo r e t h e ad c r e g i s t er co n t e n ts a r e lo ade d t o t h e s e r i al r e g i s t er (s d o fs g o in g hig h ). this defa u l t d a c lo ad p o si tio n ca n be ad van c e d in tim e t o o c c u r ea rlier wi t h r e s p ec t t o t h e s d o f s g o in g hig h . f i gur e 50 sho w s a n exam p l e o f th e ad c un lo ad an d d a c lo ad s e q u e n c e . a t t i m e t 1 , t h e s d ofs is ra is e d to indi ca te t h a t a ne w ad c w o rd is r e ad y . f o l l o w i n g t h e sd of s pu l s e, 1 6 bit s of a d c d a t a are cl o c ke d out on sd o i n t h e sub s e q u e n t 1 6 s c l k c y cl e s , f i nishi n g a t t i me t 2 w h er e t h e ds p s s p o r t has r e cei v ed t h e 16-b i t w o r d . the ds p ma y pro c e s s t h i s i n for m a t i o n a nd ge ne r a te a d a c word to b e s e n t to th e ad73322l. t i m e t 3 ma rks t h e b e g i nnin g o f t h e s e q u e n c e o f s e ndin g t h e d a c w o r d t o t h e ad73322l. this s e q u en ce en ds a t tim e t 4 , w h er e t h e d a c r e g i st er is u p da t e d f r o m t h e 16 b i ts in th e ad73322l s s e r i al reg i s t er . h o w e v e r , t h e d a c is n o t u p da te d f r o m t h e d a c r e g i ster un t i l t i me t 5 , w h ic h ma y n o t be accep t -a b l e in c e r t a i n a p pl ic a t i o n s . i n o r der t o r e d u ce t h is dela y a nd lo ad t h e d a c a t t i me t 6 , t h e d a c ad van c e r e g i s t er can b e p r og ra mm ed wi th a sui t a b le s e t t in g co r r es p o n d in g t o t h e r e q u ir e d t i me ad van c e (r efer t o t a b l e 15 fo r det a i l s o f d a c ti m i n g co n t r o l s e t t i n gs). se sclk sdofs sdo sdifs data register update dac load from dac register t 1 t 2 t 3 t 4 t 6 t 5 adc word sdi dac word 00691-048 f i gure 48. d a c timing control
ad73322l rev. a | page 41 of 48 configuring an ad73322l to operate in data mode this section describes the typical sequence of control words that are required to be sent to an ad73322l to set it up for data mode operation. 1 in this sequence, registers b, c, and a are programmed before the device enters data mode. this description refers to the steps in table 27. at each sampling event, a pair of sdofs pulses is observed, which causes a pair of control (programming) words to be sent to the device from the dsp. each pair of control words should program a single register in each channel. the sequence to be followed is channel 2 followed by channel 1. step 1 shows the first output sample event following a device reset. the sdofs signal is raised on both channels 2 simulta- neously, which prepares the dsp rx register to accept the adc word from channel 2, while sdofs from channel 1 becomes an sdifs to channel 2. as the sdofs of channel 2 is coupled to the dsps tfs and rfs, and to the sdifs of channel 1, this event also forces a new control word to be output from the dsp tx register to channel 1. 3 step 2 shows the status of the channels following the transmis- sion of the first control word. the dsp has received the output word from channel 2, while channel 2 has received the output word from channel 1. channel 1 has received the control word destined for channel 2. at this stage, the sdofs of both channels are again raised because channel 2 has received channel 1s output word, and as it is not a valid control word addressed to channel 2, it is passed on to the dsp. likewise, channel 1 has received a control word destined for channel 2 address field is not zeroand it decrements the address field of the control word and passes it on. step 3 shows completion of the first series of control word writes. the dsp has received both output words and each channel has received a control word that addresses control register b and sets the internal mclk divider ratio to 1, sclk rate to dmclk/2, and sampling rate to dmclk/256. both channels are updated simultaneously because both receive the addressed control word at the same time. this is an important factor in cascaded operation as any latency between updating the sclk or dmclk of channels can result in corrupted operation. this does not happen in the case of an fslb config- uration, as shown here, but must be taken into account in a nonfslb configuration. another observation of this sequence is that the data-words are received and transmitted in reverse orderthat is, the adc words are received by the dsp, channel 2 first, then channel 1 and, similarly, the transmit words from the dsp are sent to channel 2 first, then to channel 1. this ensures that all channels are updated at the same time. steps 4 to 6 are similar to steps 1C3, but the user must program control register c to power up the analog sections of the device (adcs, dacs, and reference). steps 7 to 9 are similar to steps 1 to 3, but the user must program control register a, with a device count field equal to two channels in cascade, and set the pgm/data bit to one to put the channel in data mode. by step 10, the programming phase completed, and actual channel data read and write can begin. the words loaded in the serial registers of the two channels at the adc sampling event contain valid adc data, and the words written to the channels from the dsps tx register are interpreted as dac words. the dsp tx register contains the dac word for channel 2. in step 11, the first dac word has been transmitted into the cascade, and the adc word from channel 2 has been read from the cascade. the dsp tx register contains the dac word for channel 1. because the words being sent to the cascade are being interpreted as 16-bit dac words, the addressing scheme changes from one where the address was embedded in the transmitted word, to one where the serial port counts the sdifs pulses. when the number of sdifs pulses received equals the value in the channel count field of control register athe length of the cascadeeach channel updates its dac register with the present word in its serial register. in step 11 each channel has received only one sdifs pulse; channel 2 received one sdifs from the sdofs of channel 1 when it sent its adc word, and channel 1 received one sdifs pulse when it received the dac word for channel 2 from the dsps tx register. therefore, each channel raises its sdofs line to pass on the current word in its serial register, and each channel receives another sdifs pulse. step 12 shows the completion of an adc read and dac write cycle. following step 11, each channel has received two sdifs pulses that equal the setting of the channel count field in control register a. the dac register in each channel is up- dated with the contents of the word that accompanied the sdifs pulse that satisfied the channel count requirement. the internal frame sync counter is reset to zero and begins counting for the next dac update cycle. steps 10C12 are repeated on each sampling event. 1 channel 1 and channel 2 refer to the two afe sections of the ad73322l. 2 the ad73322l is configure d as two channels in cascade. the internal cascade connections between channels 1 and 2 are detailed in . the connections sdi/sdifs are inputs to channel 1, while sdo/sdofs are outputs from channel 2. figure 23 3 this sequence assumes that the ds p sports rx and tx interrupts are enabled. ensure that there is no latency (separation) between control words in a cascade configuration. this is especially the case when programming control registers a and b as they must be updated synchronously in each channel.
ad73322l rev. a | page 42 of 48 table 27. data mode operation step dsp tx ad73322l channel 1 ad73322l channel 2 dsprx 1 control word crbCch2 -> data-word output ch1 -> data-word output ch2 -> 1000100100001011 0000000000000000 0000000000000000 2 control word crbCch1 -> control word crbCch2 -> data-word output ch1 -> data-word output ch2 1000000100001011 1000100100001011 0000000000000000 0000000000000000 3 control word crbCch1 control word crbCch2 data-word output ch1 1000000100001011 1000000100001011 0000000000000000 at this time, control register b of both channel 1 and channel 2 are updated. 4 control word crcCch2 -> data-word output ch1 -> data-word output ch2 -> 1000101011111001 0000000000000000 0000000000000000 5 control word crcCch1 -> control word crcCch2 -> data-word output ch1 -> data-word output ch2 1000001011111001 1000101011111001 0000000000000000 0000000000000000 6 control word crcCch1 control word crcCch2 data-word output ch1 1000001011111001 1000001011111001 0000000000000000 at this time, control register c of both channel 1 and channel 2 are updated. 7 control word craCch2 -> data-word output ch1 -> data-word output ch2 -> 1000100000010001 0000000000000000 0000000000000000 8 control word craCch1 -> control word craCch2 -> data-word output ch1 -> data-word output ch2 1000000000010001 1000100000010001 0000000000000000 0000000000000000 9 control word craCch1 control word craCch2 data-word output ch1 1000000000010001 1000000000010001 0000000000000000 at this time, control register a of both channel 1 and channel 2 are updated. 10 dac word ch 2 -> adc result ch1 -> adc result ch2 -> 0111111111111111 unknown data unknown data 11 dac word ch 1 -> dac word ch 2 -> adc result ch1 -> adc result ch2 1000000000000000 0111111111111111 unknown data unknown data 12 dac word ch 1 dac word ch 2 adc result ch1 1000000000000000 0111111111111111 unknown data at this time, the dac of both channel 1 and channel 2 is upda ted and the adc of both channel 1 and channel 2 has been read.
ad73322l rev. a | page 43 of 48 configuring an ad73322l to operate in mixed mode this section describes a typical sequence of control words that would be sent to an ad73322l to configure it for operation in mixed mode. 1 it is not intended to be a definitive initialization sequence, but shows users the typical input/output events that occur in the programming and operation phases 2 . the text in this section refers to the steps in table 28. steps 1C5 detail the transfer of the control words to control register a, which programs the device for mixed-mode operation. step 1 shows the first output sample event following a device reset. the sdofs signal is simultaneously raised on both channels, which prepares the dsp rx register to accept the adc word from channel 2, while sdofs from channel 1 becomes an sdifs to channel 2. the cascade is configured as nonfslb, which means that the dsp has control over what is transmitted to the cascade 3 and, in this case, does not transmit to the devices until both output words have been received from the ad73322l. step 2 shows the status of the channels following receipt of the channel 2 output word. the dsp has received the adc word from channel 2, while channel 2 has received the output word from channel 1. at this stage, the sdofs of channel 2 is again raised because channel 2 has received channel 1s output word and, as it is not addressed to channel 2, passes it on to the dsp. in step 3, the dsp has received both adc words. typically, an interrupt is generated following reception of the two output words by the dsp (this involves programming the dsp to use autobuffered transfers of two words). the transmit register of the dsp is loaded with the control word destined for channel 2. this generates a transmit frame-sync (tfs) that is input to the sdifs input of the ad73322l to indicate the start of transmission. in step 4, channel 1 contains the control word destined for channel 2. the address field is decremented, sdofs1 is raised (internally) and the control word is passed on to channel 2. the tx register of the dsp has now been updated with the control word destined for channel 1 (this can be done using auto- buffering of transmit or by handling transmit interrupts following each word sent). in step 5, each channel has received a control word that addresses control register a, sets the device count field equal to two channels, and programs the channels into mixed mode (mm and pmg /data set to one). following step 5, the device has been programmed into mixed mode although none of the analog sections have been powered up (controlled by control register c). steps 6 to 10 detail update of control register b in mixed mode. in steps 6 to 8, the adc samples, which are invalid because the adc section is not yet powered up, are transferred to the dsps rx section. in the subsequent interrupt service routine, the tx register is loaded with the control word for channel 2. in steps 9C10, channels 1 and 2 are loaded with a control word setting for control register b, which programs dmclk = mclk, the sampling rate, to dmclk/256, sclk = dmclk/2. steps 11 to 17 are similar to steps 6 to 12 except that control register c is programmed to power up all analog sections (adc, dac, reference = 1.2 v, refout). in steps 16C17, dac words are sent to the deviceboth dac words are necessary because each channel only updates its dac when the device has counted a number of sdifs pulses, accompanied by dac words (in mixed mode, the msb = 0), that are equal to the device count field of control register a 4 . because the channels are in mixed mode, the serial port interrogates the msb of the 16-bit word sent to determine whether it contains dac data or control information. dac words should be sent in the sequence channel 2 followed by channel 1. steps 11 to17 show the control register update and dac update in a single sample period. note that this combination is not possible in the fslb configuration 3 . steps 18 to 25 illustrate a control register readback cycle. in step 22, both channels have received a control word that addresses control register c for readback (bit 14 of the control word = 1). when the channels receive the readback request, the register contents are loaded to the serial registers, as shown in step 23. sdofs is raised in both channels, which causes these readback words to be shifted out toward the dsp. in step 24, the dsp has received the channel 2 readback word, while channel 2 has received the channel 1 readback word (note that the address field in both words has been decremented to 111b). in step 25, the dsp has received the channel 1 readback word (its address field has been further decremented to 110b). steps 26 to 30 detail an adc and dac update cycle using the nonfslb configuration. in this case, no control register update is required. 1 channel 1 and channel 2 refer to the two afe sections of the ad73322l. 2 this sequence assumes that the ds p sports rx and tx interrupts are enabled. ensure there is no latency (separation) between control words in a cascade configuration. this is espe cially the case when programming control registers a and b. 3 mixed-mode operation with the fslb conf iguration is more restricted in that the number of words sent to the cascade equals the number of channels in the cascade. this means that dac updates may need to be substituted with a register write or read. using the fslb configuration introduces a corruption of the adc samples in the sample period following a control register write. this corruption is predictable and ca n be corrected in the dsp. the adc word is treated as a control word and the device address field is decremented in each channel that it passes through before being returned to the dsp. 4 in mixed mode, dac update is done using the same sdifs counting scheme as in normal data mode, with the exception that only dac words (msb set to zero) are recognized as being able to increment the frame sync counters.
ad73322l rev. a | page 44 of 48 table 28. mixed mode operation step dsp tx ad73322l channel 1 ad73322l channel 2 dsp rx 1 output ch1 -> output ch2 -> 0000000000000000 0000000000000000 2 output ch1 -> output ch2 0000000000000000 0000000000000000 3 cra-ch2 -> output ch1 1000100000010011 0000000000000000 4 cra-ch1 -> cra-ch2 -> 1000000000010011 1000100000010011 5 cra-ch1 cra-ch2 1000000000010011 1000000000010011 control register a of both channels has been programmed. 6 adc result ch1 -> adc result ch2 -> unknown data unknown data 7 adc result ch1 -> adc result ch2 unknown data unknown data 8 crb-ch2 -> adc result ch1 1000100100001011 unknown data 9 crb-ch1 -> crb-ch2 -> 1000000100001011 1000100100001011 10 crb-ch1 crb-ch2 1000000100001011 1000000100001011 the adc data from both channels has been read and control register b of both channels has been programmed. 11 adc result ch1 -> adc result ch2 -> unknown data unknown data 12 adc result ch1 -> adc result ch2 unknown data unknown data 13 crc-ch2 -> adc result ch1 1000101011111001 unknown data 14 crc-ch1 -> crc-ch2 -> 1000001011111001 1000101011111001 15 dac word ch 2 -> crc-ch1 crc-ch2 0111111111111111 1000001011111001 1000001011111001 16 dac word ch 1 -> dac word ch 2 -> 1000000000000000 0111111111111111 17 dac word ch 1 dac word ch 2 1000000000000000 0111111111111111 the adc data from both channels has been read, control register c of both channels has been programmed, and dac data for both channels has been written. 18 adc result ch1 -> adc result ch2 -> unknown data unknown data 19 adc result ch1 -> adc result ch2 unknown data unknown data 20 crc-ch2 -> adc result ch1 11001010xxxxxxxx unknown data 21 crc-ch1 -> crc-ch2 -> 10000010xxxxxxxx 11001010xxxxxxxx 22 crc-ch1 crc-ch2 10000010xxxxxxxx 10000010xxxxxxxx 23 readback ch 1 -> readback ch 2 -> 1100001011111001 1100001011111001
ad73322l rev. a | page 45 of 48 step dsp tx ad73322l channel 1 ad73322l channel 2 dsp rx 24 readback ch 1 -> readback ch 2 1111101011111001 1111101011111001 25 readback ch 1 1111001011111001 the adc data of both channels has been read, and a readback of control register c has been performed. 26 adc result ch1 -> adc result ch2 -> unknown data unknown data 27 adc result ch1 -> adc result ch2 unknown data unknown data 28 dac word ch 2 -> adc result ch1 0111111111111111 unknown data 29 dac word ch 1 -> dac word ch 2 -> 1000000000000000 0111111111111111 30 dac word ch 1 dac word ch 2 1000000000000000 0111111111111111 the adc data from both channels has been read, and the dac data for both channels has been written.
ad73322l rev. a | page 46 of 48 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ae 0.33 (0.0130) 0.20 (0.0079) 8 0 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 1.27 (0.0500) bsc 28 15 14 1 18.10 (0.7126) 17.70 (0.6969) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) coplanarity 0.10 f i gure 49. 28-l ead standar d s m all o u tline p a ck age [s oi c ] w i de body (r w - 28) di me nsio ns sho w n i n mi ll im e t e r s a n d (i nc he s ) 28 15 14 1 8 0 compliant to jedec standards mo-153ae seating plane coplanarity 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 f i gure 50. 2 8 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 28) di me nsio ns sho w n i n mi ll im e t e r s view a top view (pins down) 11 1 44 34 33 23 22 12 1.00 bsc lead pitch lead width 16.00 bsc sq 14.00 bsc sq 1.60 max 0.75 0.60 0.45 0.50 0.42 0.35 pin 1 0.20 0.09 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 10 6 2 7 3. 5 0 0.15 0.05 compliant to jedec standards ms-026-bea f i g u re 51. 4 4 -l ead l o w p r of i l e q u ad f l at p a ckag e [l qf p ] (st - 44-2) di me nsio ns sho w n i n mi ll im e t e r s
ad73322l rev. a | page 47 of 48 ordering guide model temperature range package description package option ad73322lar ? 40c to +85c wide body soic rw-28 AD73322LAR-REEL ? 40c to +85c wide body soic rw-28 AD73322LAR-REEL7 ? 40c to +85c wide body soic rw-28 ad73322laru ? 40c to +85c thin shrink tssop ru-28 ad73322laru-reel ? 40c to +85c thin shrink tssop ru-28 ad73322laruz 1 ? 40c to +85c thin shrink tssop ru-28 ad73322laruz-reel 1 ? 40c to +85c thin shrink tssop ru-28 ad73322last ? 40c to +85c plastic thin quad flatpack (lqfp) st-44a ad73322last-reel ? 40c to +85c plastic thin quad flatpack (lqfp) st-44a ad73322lyr ?40c to +105c wide body soic rw-28 ad73322lyr-reel ?40c to +105c wide body soic rw-28 ad73322lyr-reel7 ?40c to +105c wide body soic rw-28 ad73322lyru ?40c to +105c thin shrink tssop ru-28 ad73322lyru-reel ?40c to +105c thin shrink tssop ru-28 ad73322lyst ?40c to +105c plastic thin quad flatpack (lqfp) st-44a ad73322lyst-reel ?40c to +105c plastic thin quad flatpack (lqfp) st-44a 1 z = pb-free part.
ad73322l rev. a | page 48 of 48 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c00691C0 C 12/04(a)

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